DP8344 datasheet(52/184 Pages) NSC

52 / 184 page

30 Transceiver (Continued)

321 Transmitter

The transmitter accepts parallel data from the CPU formats

it according to the desired protocol and transmits it as a

serial biphase-encoded bit stream A block diagram of the

transmitter logic is shown in

Figure 3-6 Two biphase out-

puts DATA-OUT DATA-DLY and the external line driver

enable TX-ACT provide the data and control signals for the

external line interface circuitry The two biphase outputs are

valid only when TX-ACT is asserted (high) and provide the

necessary phase relationship to generate the ‘‘predistor-

tion’’ waveform common to all of the transceiver protocols

See

Figure 3-7 for the timing relationships of these outputs

as well as the output of the line driver For a recommended

32703299 coax interface see Section 3251 3270 Line

Interface For a recommended 5250 twinax interface see

Section 3252 5250 Line Interface

The capability is provided to invert DATA-OUT and DATA-

DLY via the Transmitter Invert bit

TIN

located in the

Transceiver Mode Register

TMR

In addition the timing

relationship between TX-ACT and the two biphase outputs

can be modified with the Advance Transmitter Active con-

trol ATA When ATA is cleared low (the power-up condi-

tion) the transmitter generates exactly five line quiesce bits

at the start of each message as shown in

Figure 3-7 If

ATA is asserted high the transmitter generates a sixth line

quiesce bit adding one biphase bit time to the start se-

quence transmission The line driver enable TX-ACT is as-

serted halfway through this bit time allowing an additional

half-bit to precede the first full line quiesce of the transmit-

ted waveform Also the state of DATA-DLY is such that no

predistortion results on the line during this first half line

quiesce This modified start sequence is depicted in the dot-

ted lines shown in

Figure 3-7 and is used to limit the initial

transient voltage amplitude when the message begins

Data is loaded into the transmitter by writing to the Receive

Transmit Register RTR

causing the first location of the

FIFO to be loaded with a 12-bit word (8 bits from RTR and

4 bits from the Transceiver Command Register TCR

The

data byte to be transmitted is loaded into

RTR

and

TCR contains additional information required by the pro-

tocol It is important to note that if TCR is to be changed

it must be loaded before RTR

A multi-frame transmission

is accomplished by sequentially loading the FIFO with the

required data the transmitter taking care of all necessary

frame formatting

If the FIFO was previously empty indicated by the Transmit

FIFO Empty flag TFE being asserted the first word loaded

into the FIFO will asynchronously propagate to the last loca-

tion in approximately 40 ns leaving the first two locations

empty It is therefore possible to load up the FIFO with three

sequential instructions at which time the Transmit FIFO Full

flag TFF will be asserted If RTR is written while TFF is

high the first location of the FIFO will be over-written and

that data will be destroyed

When the first word is loaded into the FIFO the transmitter

starts up from idle asserting TX-ACT and the Transmitter

Active flag TA

and begins generating the start sequence

After a delay of approximately 16 TCLK cycles (2 biphase

bit times) the word in the last location of the FIFO is loaded

into the encoder and prepared for transmission If the FIFO

was full

TFF will be de-asserted when the encoder is

loaded allowing an additional word to be loaded into the

FIFO

When the last word in the FIFO has been loaded into the

encoder TFE goes high indicating that the FIFO is empty

To ensure the continuation of a multi-frame message more

data must then be loaded into the FIFO before the encoder

starts the transmission of the last bit of the current frame

(the frame parity bit for 3270 3299 and 8-bit modes the

last of the three mandatory fill bits for 5250) This maximum

load time from TFE can be calculated by subtracting two

from the number of bits in each frame of the respective

protocol and multiplying that result by the bit rate This

number represents the best case time to loadthe worst

case value is dependent on CPU performance Since the

CPU samples the transceiver flags and interrupts at instruc-

tion boundaries the CPU clock rate wait states (from pro-

grammed wait states asserting the WAIT pin or remote ac-

cess cycles) and the type of instruction currently being exe-

cuted can affect when the flag or interrupt is first presented

to the CPU

If there is no further data to transmit (or if the load window is

missed) the ending sequence (327032998-bit) is generat-

ed and the transmitter returns to idle de-asserting TX-ACT

and TA

In 5250 mode the three required fill bits are sent

and TX-ACT and TA are de-asserted at a time dependent

on the value of bits 7 through 3 of the Auxiliary Transceiver

If ATR 7–3

00000 TX-ACT and TA

are de-asserted at the end of the third required fill bit result-

ing in no additional ‘‘line hold’’ at the end of the message

Each increment of ATR 7–3

results in an additional half

bit time of line hold up to a maximum of 155 bit times

Data should not be loaded into the FIFO after the transmit-

ter is committed to ending the message and before the TA

flag is deasserted If this occurs the load will be missed by

the transmitter control logic and the word(s) will remain in

the FIFO This condition exists when TA and TFE are

both low at the same time and can be cleared by resetting

the transceiver (asserting TRES ) or by loading more data

into the FIFO in which case the first frame(s) transmitted

will contain the word(s) left in the FIFO from the previous

message

DP8344 Datasheet(PDF) 52 Page - National Semiconductor (TI)

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