DP8344 datasheet(35/184 Pages) NSC

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20 CPU Description (Continued)

lowing the instruction after the write to

DCR

A write to

DCR 2–0

to change the number of data wait states will

take effect on the next data memory access instruction

even if it immediately follows the write to

DCR

A write to DCR 2–0

to change the number of data wait

states or to ACR 4TR

will take effect on the next data

memory access instruction even if it immediately follows

write to

DCR

ACR

Both instruction and data

wait states cause the insertion of additional T-states prior to

T2 and these T-states are referred to as TW The purpose

of instruction wait states is to increase the time from instruc-

tion address generation to the beginning of the next instruc-

tion cycle Data wait states increase the time from data

memory address generation to the removal of the strobe at

the end of data memory access instructions Therefore in-

struction and data wait states are counted concurrently in a

data memory access instruction and TX of a data memory

access instruction is counted as one instruction wait state

The actual number of wait states added to a data memory

access is calculated as the maximum between the

number of data wait states and one less than the number of

instruction wait states

Figure 2-21 shows a write of data

memory with one wait state This could be accomplished by

selecting two instruction wait states or one data wait state

The effect of the wait state is to increase the time the write

strobe is active and the data is valid on AD The same situa-

tion for a read of data memory is shown in

Figure

2-22 Note that if 4TR is set to one then one data wait

state has no additional affect on a read of data memory and

the timing is the same as shown in

Figure 2-18 The affect of

two data memory wait states and 4TR set to one is shown

Figure 2-23 A two T-state instruction with two instruction

wait states is shown in

Figure 2-24 and a four T-state in-

struction with one instruction wait state is shown in

Figure

2-25 As stated earlier instruction wait states are inserted

before T2 Adding wait states to a four T-state two word

instruction causes the wait states to count twice when cal-

culating total instruction cycle time The wait states are add-

ed to each of the two words of the instruction

TLF9336 – E4

FIGURE 2-21 Data Memory Write with One Wait State

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