DP8344 datasheet(45/184 Pages) NSC

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20 CPU Description (Continued)

A call to the interrupt address is generated when an inter-

rupt is detected by the CPU The address for each interrupt

is constructed by concatenating the Interrupt Base Register

IBR

contents with the individual interrupt code as shown

in Table 2-28 There is room between the interrupt address-

es for a maximum of four instruction words

TABLE 2-28 Interrupt Vector Generation

Interrupt

Code

NMI

111

RFF DA RA

001

TFE

010

LTA

011

BIRQ

100

101

Interrupt Vector

IBR Contents

Code

Interrupts are sampled by each falling edge of the CPU

clock with the last falling edge prior to the start of the next

instruction determining whether an interrupt will be process-

ed The timing of a typical interrupt event is shown in

Figure

2-34 The interrupt occurs during the current instruction and

is sampled by the falling edge of the CPU clock The next

instruction is not operated on and its address is stored in the

internal address stack along with GIE

the ALU flags and

the register bank positions The address stack is twelve

words deep A two T-state internal call is now executed in

place of the non-executed instruction This call will cause a

branch to the interrupt address that is generated in the first

half of T-state T1 Also

GIE is cleared at the end of the

first half of T-state T1 The internal call to the interrupt ad-

dress is subject to instruction wait states as configured in

DCR

224 Oscillator

The crystal oscillator is an on-chip amplifier which may be

used with an external crystal to generate accurate CPU and

transceiver clocks The input to this amplifier is X1 pin 33

The output of the amplifier is X2 pin 34 When X1 and X2

are connected to a crystal and external capacitors

(Figure

2-35) the combined circuit forms a Pierce crystal oscillator

with the crystal operating at parallel resonance Crystals

that oscillate over the frequency range of 2 MHz to 20 MHz

may be used The recommended crystal parameters for op-

eration with the oscillator are given in Table 2-29 The exter-

nal capacitor values should be chosen to provide the manu-

facturer’s specified load capacitance for the crystal when

combined with the parasitic capacitance of the trace sock-

et and package As an example a crystal with a specified

load capacitance of 20 pF used in a circuit with 13 pF per

pin parasitic capacitance will require external capacitor val-

ues of 27 pF each This provides an equivalent capacitance

of 40 pF on each side of the crystal and has a 20 pF series

equivalent value across the crystal

As an alternative to the crystal oscillator an external clock

source may be used In this case the external clock source

should be connected to X1 and no external circuitry should

be connected to X2

(Figure 2-36) The DP8344 can supply a

clock source equal in frequency to the crystal oscillator or

external clock source to other circuitry via pin 35 the CLK-

OUT output This output is a buffered version of the signal at

TABLE 2-29 Recommended Crystal Parameters

AT Cut Parallel Resonant

Fundamental Mode

Load Capacitor e 20 pF

Series Resistance k 20X

Frequency Tolerance 0005% at 25 C

Stability 001% 0 –70 C

Drive Level 05 mW Typical

TLF9336 – F7

FIGURE 2-34 Interrupt Timing

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