DP8344 datasheet(63/184 Pages) NSC

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40 Remote Interface and Arbitration System (RIAS) (Continued)

TABLE 4-1 RIAS Inputs and Outputs

Signal

InOut

Reset

Function

State

CMD

oMmanD input When high remote accesses are directed to the

Remote Interface Configuration register

RIC

When low remote

accesses are directed to Data Memory Instruction Memory or the

Program Counter as determined by RIC 10

LCL

Out

oCaL Normally low goes high when the BCP relinquishes the data

and address bus to service a remote access

LOCK

Asserting this input Low will LOCK out local (BCP) accesses to Data

Memory Once the remote processor has been granted the bus

LOCK gives it sole access to the bus and BCP accesses are

‘‘waited’’

RAE

emote Access Enable Setting this input low allows host access of

BCP functions and memory

REM-RD

REM

ote ReaD When low along with RAE a remote read cycle is

requested serviced by the BCP when the data bus becomes

available

REM-WR

REM

ote WRite When low along with RAE a remote write cycle is

requested serviced by the BCP when the data bus becomes

available

WR-PEND

Out

ite PENDing In a system configuration where remote write

cycles are latched WR-PEND will go low indicating that the latches

contain valid data which have yet to be serviced by the BCP

XACK

Out

Transfer ACKnowledge Normally high goes low on REM-RD or

REM-WR going low (if RAE low) returning high when the transfer is

complete Normally used as a ‘‘wait’’ signal to a remote processor

(In the Latched Write mode XACK will only transition if a second

remote access begins before the first one completes)

WAIT

Asserting this input low will add wait states to both remote accesses

and to the BCP instruction cycle WAIT will extend a remote access

until it is set high

BIS SS FBW LR LW STRT MS1 MS0 RIC

BIS

Bidirectional Interrupt Status

Single-Step

FBW

Fast Buffered Write mode

Latched Read mode

Latched Write mode

STRT

BCP CPU startstop

MS1 – 0

Memory Selection

FIGURE 4-2 Remote Interface Control Register

411 Remote Arbitration Phases

The BCP CPU and RIAS share the internal CPU-CLK This

clock is derived from the X1 crystal input It can be divided

by two by setting CCS e 1in DCR or run undivided by

setting CCS e 0 The frequency at which the Remote

Processor is run need not bear any relationship to the CPU-

CLK A remote access is treated as an asynchronous event

and data is handshaked between the Remote Processor

and the BCP

The two key handshake signals involved in the BCPRP

interface are Transfer Acknowledge (XACK) and Local

(LCL) Internally two more signals control the access tim-

ing INT-READ and INT-WRITE The timing for a generic

Remote Access is shown in

Figure 4-3 A remote access is

TLF9336 – 20

FIGURE 4-3 Generic Remote Access (RAE e 0)

initiated by the RP asserting REM-RD or REM-WR with RAE

low There is no set-uphold time relationship between RAE

and REM-RD or REM-WR These signals are internally gat-

ed together such that if RAE (REM-RD a REM-WR) is true

a remote access will begin A short delay later XACK will

fall This signal can be fed back to the RP’s wait line to

extend its read or write cycle if necessary When the BCP’s

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