DP8344 datasheet(82/184 Pages) NSC

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40 Remote Interface and Arbitration System (RIAS) (Continued)

state and A and AD continue to be tri-stated This allows the

Remote Processor to drive the Data Memory address and

data buses for the write Since DMEM is subject to wait

states RSD4 is looped upon until all the programmed Data

Memory wait states have been inserted

The last possible Memory Selection is Instruction Memory

MS1–0 e 01 The two possible next states for IMEM de-

pend on whether RASM is expecting the low byte or high

byte Instruction words are accessed low byte then high

byte and RASM powers up expecting the low Instruction

byte The internal flag that keeps track of the next expected

Instruction byte is called the High Instruction Byte flag (HIB)

If HIB is low the next state is RSD5 and the low instruction

byte is written into the holding register ILAT If HIB is high

the high instruction byte is moved to I15 – 8 and ILAT is

moved to I7 – 0 At the same time IWR is asserted low be-

ginning the write to instruction memory An IMEM access

like a DMEM access is subject to wait states and these

states will be looped on until all programmed instruction

memory wait states have been inserted

Note

Resetting the BCP will reset HIB (ie

HIB e 0) Writing 01 to the

Memory Select bits in RIC (ie

MS1–0 e 01 pointing to IMEM)

will also force HIB to zero This way the instruction word boundary

can be reset without resetting the BCP

After all of the programmed wait states are inserted into

RSD states more wait states may be added by asserting

WAIT low a half T-state before the end of the last pro-

grammed wait state If there are no programmed wait states

WAIT must be asserted low a half T-state before the end of

RSD to add wait states If WAIT remains low the remote

access is extended indefinitely All the RSD states converge

to state RSE on the next CPU-CLK after the programmed

wait state conditions are met and WAIT is high LCL remains

high in all RSE states and A and AD remain in TRI-STATE

as well XACK returns high in this state indicating that the

data is written and the cycle can be terminated by the RP

This state begins the Termination Phase

On the next clock the state machine will enter RSF and LCL

will return low The A and AD buses remain in TRI-STATE

for the first half T-state of RSF After the first half of RSF

the Remote Processor is no longer using the buses and the

BCP CPU can make an access to Data Memory by asserting

LCL-BREQ If a local bus request is made a local bus grant

will be given to the Timing Control Unit If the preceding

access was a write of IMEM then HIB is switched and if the

access was to the high byte of IMEM then the PC is incre-

mented If RAE REM-WR is deasserted at this point the

next clock will bring RASM back to RSA where it will loop

until another remote access is initiated RSG is entered if

RAE REM-WR is still true RASM will loop in RSG until

RAE REM-WR is no longer active at which time the state

machine will return to RSA

Figure 4-21 the BCP is executing the first of two Data

Memory writes when REM-WR goes low In response

XACK goes low waiting the Remote Processor At the end

of the first instruction although the BCP begins its second

write by taking ALE high RASM now takes control of the

bus and deasserts LCL high at the end of T1 A one T-state

delay is built into this transfer to ensure that WRITE has

been deasserted high before the data bus is switched The

Timing Control Unit is now waited inserting remote access

wait states TWr as RASM takes over

The remote access is permitted one T-state to settle on the

BCP address bus before WRITE goes low XACK then re-

turns high one T-state plus the programmed Data Memory

wait state TWd later having satisfied the memory access

time WRITE returns high at the same time and one T-state

later LCL returns low transferring bus control back to the

BCP The remote processor responds to XACK returning

high by deasserting REM-WR high although by this time the

BCP is well into its own memory write

DP8344 Datasheet(PDF) 82 Page - National Semiconductor (TI)

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