DP8344 datasheet(29/184 Pages) NSC

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20 CPU Description (Continued)

Several conditions apply to these flags independent of their

operation and the way they are calculated These conditions

are

1 A flag’s previous state is retained when an instruction has

no affect on that flag

2 Direct reading and writing of all ALU flags is possible via

the CCR register

3 Currrent flag values are saved onto the address stack

during interrupt and call operations and can be restored

to their original values if a return instruction with the re-

store flags option is executed

4 Flag status is calculated in parallel with the instruction

result therefore no time penalty is associated with flag

operation

When performing single byte arithmetic (ie the values are

completely represented in one byte) the Add (ADDADDA)

and Subtract (SUBSUBA) instructions should be used but

when performing multi-byte arithmetic the Add with Carry

(ADCA) and Subtract with Carry (SBCA) instructions should

be used This is because the carry (in an add operation) or

the borrow (in a subtract operation) must be carried forward

to the higher order bytes

Figure 2-11 demonstrates an in-

struction sequence for a 16-bit add and an instruction se-

quence for a 16-bit subtract

Assume the 16-bit variable X is represented by the reg-

ister pair R4(MSB) R5(LSB) and that the 16-bit variable

Y is represented by the register pair R6(MSB) R7(LSB)

To perform the assignment Y e X a Y

MOVE

R7A

GET LSB OF Y

ADDA

R5R7

Y(LSB)

4X(LSB)0Y(LSB)

MOVE

R6A

GET MSB OF Y

ADCA

R4R6

Y(MSB)

4X(MSB)0Y(MSB)

0CARRY

To perform the assignment Y e X

1 Y

MOVE

R7A

GET LSB OF Y

SUBA

R5R7

Y(LSB)

4X(LSB)1Y(LSB)

MOVE

R6A

GET MSB OF Y

SBCA

R4R6

Y(MSB)

4X(MSB)1Y(MSB)

1CARRY

FIGURE 2-11 Multi-Byte Arithmetic

Instruction Sequences

When using the ALU to perform comparisons the program-

mer has two options If the compare is to a constant value

then the CMP instruction can be used else one of the sub-

tract instructions must be used When determining the re-

sults of any compare the programmer must keep in mind

whether they are comparing signed or unsigned values Ta-

ble 2-22 lists the Boolean condition that must be met for

unsigned comparisons and Table 2-23 lists the Boolean

condition that must be met for signed comparisons

TABLE 2-22

Unsigned Comparison Results

Comparison x b y

Boolean Condition

x k yC

x s yC

l Z

x e yZ

x t yC

x l yC

Note

logical AND

l e logical OR

one’s complement

TABLE 2-23

Signed Comparison Results

Comparison x b y

Boolean Condition

x k y

(NV)

l (N V)

x s yZ

l (NV) l (N V)

x e yZ

X t y

(NV)

l (N V)

x l y

(NVZ)

l (N V Z)

Note

logical AND

l e logical OR

one’s complement

222 Timing

Timing on the BCP is controlled by an internal oscillator and

circuitry that generates the internal timing signals This cir-

cuitry in the CPU is referred to as Timing Control The inter-

nal timing of the CPU is synchronized to an internal clock

called the CPU clock CPU-CLK A period of CPU-CLK is

referred to as a T-state The clock for the BCP is provided

by a crystal connected between X1 and X2 or from a clock

source connected to X1 This clock will be referred to as the

oscillator clock OCLK The frequency of OCLK is divided in

half when the CPU clock select bit

CCS

in the Device

Control Register

DCR

is set to a one Either OCLK or

OCLK2 is used by Timing Control to generate CPU-CLK

and other synchronous signals used to control the CPU tim-

ing

After the BCP is reset CCS is high and CPU-CLK is gener-

ated from OCLK2 Since the output of the divider that cre-

ates OCLK2 can be high or low after reset CPU-CLK can

also be in a high or low state Therefore the exact number

of clock cycles to the start of the first instruction cannot be

determined Automatic test equipment can synchronize to

the BCP by asserting RESET as shown in

Figure 2-12 The

falling edge of RESET generates a clear signal which caus-

es CPU-CLK to fall The next rising edge of X1 removes the

clear signal from CPU-CLK The second rising edge of X1

will cause CPU-CLK to rise and the relationship between X1

and CPU-CLK can be determined from this point

Writing a zero to CCS causes CPU-CLK to switch from

OCLK2 to OCLK The transition from OCLK to OCLK2

occurs following the end of the instruction that writes to

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