DP8344 datasheet(54/184 Pages) NSC

54 / 184 page

30 Transceiver (Continued)

TLF9336 – 46

FIGURE 3-8 Timing of Receiver Flags Relative to Incoming Data

ister LJMP conditional and LCALL conditional) will result in

popping the last location of the FIFO presenting a new

word (if present) for future CPU access Data in the FIFO

will propagate from one location to the next in approximate-

ly 10 – 15 ns therefore the CPU is easily able to unload the

FIFO with a set of consecutive instructions

If the received bit stream is a multi-byte message the re-

ceiver will continue to process the data and load the FIFO

After the third load (if the CPU has not accessed the FIFO)

the Receive FIFO Full flag RFF will be asserted The prop-

agation delay from the occurrence of the mid-bit edge of the

parity bit of the frame to RFF being set is approximately 5

transceiver clock cycles If there are more than 3 frames in

the incoming message the CPU has approximately one

frame time (sync bit to start of parity bit) to start unloading

the FIFO Failure to do so will result in an overflow error

condition and a resulting loss of data (see Receiver Errors)

If there are no errors detected the receiver will continue to

process the incoming frames until the end of message is

detected The receiver will then return to an inactive state

clearing

and asserting the Line Turn-Around flag

LTA indicating that a message was received with no er-

rors The propagation delay from the occurrence of the

edge starting the first minicode violation to RA cleared and

LTA set is approximately 17 transceiver clock cycles in

3270 3299 and 8-bit modes In 5250 modes the assertion

of LTA and clearing of RA are dependent on how the

transmission line ends after the transmission of the three

required fill bits (see 5250 Modes) For the 3270 and 3299

protocols LTA can be used to initiate an immediate trans-

mitter FIFO load for the other protocols an appropriate re-

sponse delay time may be needed LTA is cleared by load-

ing the transmitter’s FIFO writing a one to LTA in the Net-

work Command flag register or by asserting TRES

Receiver Errors

If the Receiver Active flag RA is asserted by the receiver

logic the selected receiver input source is continuously

checked for errors which are reported to the CPU by assert-

ing the Receiver Error flag

and setting the appropri-

ate receiver error flag in the Error Code Register ECR

Ifa

condition occurs which results in multiple errors being creat-

ed only the first error detected will be latched into ECR

Once an error has been detected and the appropriate error

flag has been set the receiver is disabled clearing RA

and preventing the Line Turn-Around flag and interrupt

LTA from being asserted The Line Active flag LA re-

mains asserted if signal transitions continue to be detected

on the input

5 error flags are provided in ECR

765

rsv

OVF

PAR

IES

LMBT

RDIS

OVF

Overflow

Asserted when the decoder writes to

the first location of the FIFO while RFF is assert-

ed The word in the first location will be over-writ-

ten there will be no effect on the last two loca-

tions

PAR

Parity Error

Asserted when a received frame

fails an even (word) parity check

IES

Invalid Ending Sequence

Asserted during an

expected end sequence when an error occurs in

the mini code-violation Not valid in 5250 modes

LMBT

Loss of Mid-Bit Transition

Asserted when the

expected biphase-encoded mid-bit transition does

not occur within the expected window Indicates a

loss of receiver synchronization

RDIS

Receiver Disabled While Active

Asserted when

an active receiver is disabled by the transmitter be-

ing activated

To determine which error has occurred the CPU must read

ECR

This is accomplished by asserting the Select Error

Codes control bit SEC and reading RTR

The ECR is

only 5 bits wide therefore the upper 3 bits are still the out-

put of the receive FIFO (see

Figure 3-6) All instructions with

ECR as the source (except BIT CMP JRMK JMP regis-

ter LJMP conditional and LCALL conditional) will clear the

error condition and return the receiver to idle allowing the

receiver to again monitor the incoming data stream for a

new start sequence The SEC control bit must be de-as-

serted to read the FIFO’s data from RTR

If data is present in the FIFO when the error occurs the

Data Available flag DAV is de-asserted when the error is

detected and re-asserted when ECR is read Data pres-

ent in the FIFO before the error occurred is still available to

the CPU The flexibility is provided therefore to read the

error type and still recover data loaded into the FIFO before

the error occurred The Transceiver Reset

TRES can be

asserted at any time clearing both Transceiver FIFOs and

the error flags

DP8344 Datasheet(PDF) 54 Page - National Semiconductor (TI)

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