DP8344 datasheet(9/184 Pages) NSC

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10 Communications Processor Introduction (Continued)

12 INTERNAL ARCHITECTURE INTRODUCTION

The DP8344B Biphase Communications Processor (BCP) is

divided into three major functional blocks the Transceiver

the Central Processing Unit (CPU) and the Remote Inter-

face and Arbitration System RIAS

Figure 1-3 shows how

these blocks are related to each other and to other system

components

The transceiver consists of an asynchronous transmitter

and receiver which can communicate across a serial data

path The transmitter takes parallel data from the CPU and

appends to it the appropriate framing information The re-

sulting message is shifted out and is available as a serial

data stream on two output pins The receiver shifts in serial

messages strips off the framing information and makes the

data available in parallel form to the CPU The framing infor-

mation supplied by the BCP provides the proper message

format for several popular communication protocols These

include IBM 3270 3299 and 5250 as well as a general

purpose 8-bit mode

The transceiver clock may be derived from the internal os-

cillator either directly or through internal divide-down circuit-

ry There is also an input for an external transceiver clock

thus allowing complete flexibility in the choice of data rates

The receiver input can come from three possible sources

There is a built-in differential amplifier which is suitable for

most line interfaces a single-ended digital input for use with

an external comparator and an internal loopback path for

self testing Refer to the Transceiver section for a detailed

description of all transmitter and receiver functions and to

the application note on coax interfaces for the proper use of

the differential amplifier

The CPU is a general purpose 8-bit microprocessor capa-

ble of 20 MHz operation It has a reduced instruction set

which is optimized for transceiver and data handling per-

formance It also has a full function arithmeticlogic unit

(ALU) which performs addition subtraction Boolean opera-

tions rotations and shifts Separate instruction and data

memory systems are supported each with 16-bit address

buses for a total of 64k address space in each

There are 44 internal registers accessible to the CPU

These include special configuration and control registers for

the transceiver and processor four 16-bit indices to data

memory and 20 8-bit general purpose registers There is

also a 16-bit timer and a 16-byte deep LIFO data stack

which are accessible in the register address space For

more detailed information see the specific sections on the

The BCP can operate independently or with another proces-

sor as the host system If such a system is required com-

munication with the BCP is possible by sharing data memo-

ry The Remote Interface controls bus arbitration and ac-

cess to data memory as well as program up-loading and

execution For example it is possible for a host system to

load the BCP’s instruction memory and begin program exe-

cution then pass data back and forth through data memory

accesses The section on the Remote Interface and Arbitra-

tion System provides all of the necessary timing and control

information to implement an interface between a BCP and a

remote system

As shown in

Figure 1-4 the BCP uses two entirely separate

memory systems one for program storage and the other for

data storage This type of memory arrangement is referred

to as Harvard architecture Each system has 16 address

lines for a maximum of 64k words in each and its own set

of data lines The instruction (program) memory is two bytes

(16 bits) wide and the data memory is one byte (8 bits)

wide

In order to reduce the number of pins required for these

signals the address and data lines for data memory are

multiplexed together This requires an external latch and the

Address Latch Enable signal (ALE) for de-multiplexing

TLF9336 – B9

FIGURE 1-3 Simplified Block Diagram

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