DP8344 datasheet(46/184 Pages) NSC

46 / 184 page

20 CPU Description (Continued)

TLF9336 – F8

FIGURE 2-35 DP8344B Operation with Crystal

TLF9336 – F9

FIGURE 2-36 DP8344B Operation with External Clock

30 Transceiver

31 TRANSCEIVER ARCHITECTURAL DESCRIPTION

The transceiver section operates as an on-chip indepen-

dent peripheral implementing all the necessary formatting

required to support the physical layer of the following serial

communications protocols

IBM 3270 (including 3299)

IBM 5250

NSC general purpose 8-bit

The CPU and transceiver are tightly coupled through the

CPU register space with the transceiver appearing to the

CPU as a group of special function registers and three dedi-

cated interrupts The transceiver consists of separate trans-

mitter and receiver logic sections each capable of indepen-

dent operation communicating with the CPU via an asyn-

chronous interface This interface is software configurable

for both polled and interrupt-driven interaction allowing the

system designer to optimize his product for the specific ap-

plication

The transceiver connects to the line through an external line

interface circuit which provides the required DC and AC

drive characteristics appropriate to the application A block

diagram of such an interface is shown in

Figure 3-1 An on-

chip differential analog comparator optimized for use in a

transformer coupled coax interface is provided at the input

to the receiver Alternatively if an external comparator is

necessary the input signal may be routed to the DATA-IN

TLF9336 – 33

FIGURE 3-1 System Block Diagram Showing Details of the Line Interface

DP8344 Datasheet(PDF) 46 Page - National Semiconductor (TI)