DP8344 datasheet(97/184 Pages) NSC

97 / 184 page

50 Device Specifications (Continued)

55 SWITCHING CHARACTERISTICS

The following specifications apply for VCC e 45V to 55V

TA e 0 Cto70 C

551 Definitions

The timing specifications for the BCP are provided in the

following tables and figures The tables consist of five sec-

tions which are the following the timing parameter symbol

the parameter ID

the parameter description the formula

for the parameter and the timing specification for the pa-

rameter Below each table is a figure containing the wave-

forms for the parameters in the table

The parameter symbol is composed of the type of timing

specification and the signal or signals involved Note that

the symbols are unique only within a given table The follow-

ing symbol conventions are used for the type of timing spec-

ification

Pulse width specification

tPD

Propagation delay specification

Hold time specification

tSU

Setup time specification

tZA

High impedance to active delay specification

(enable time)

tAZ

Active to high impedance delay specification

(disable time)

tACC

Access time specification

Clock period specification

The parameter ID

is used to cross reference the timing

parameter to the appropriate timing relationship in the ac-

companying figure The waveforms in the figures are shown

with the CPU clock running full speed ( CCS e 0) For this

case CPU-CLK and CLK-OUT are equivalent If CPU-CLK

2 is selected ( CCS e 1) the effect on the waveforms with

CLK-OUT is for CLK-OUT to double in frequency The same

is true for waveforms with X1 Note that CLK-OUT is always

running at the crystal frequency and it is the CPU-CLK that

is changing to half speed

The parameter description defines the timing relationship

being specified BCP pin references are capitalized in the

description

Many of the timing specifications are dependent on vari-

ables such as operating frequency and number of pro-

grammed wait states The formula for the parameter allows

an accurate timing specification to be calculated for any

combination of these variables The formula represents the

part of the timing specification that is synchronized to the

internal CPU clock This value is calculated and then added

to the value specified under the Min or Max column to cre-

ate the minimum or maximum guaranteed timing specifica-

tion for the parameter

The following acronyms are used in the tables

DMEM refers to data memory

IMEM refers to instruction memory

RIC refers to the Remote Interface Control register

PC refers to the BCP Program Counter

T refers to the CPU clock period in ns

TH refers to first half pulse width (high time) of the CPU

clock in ns

TL refers to second half pulse width (low time) of the

CPU clock in ns

C refers to the transceiver clock period in ns

nIW is the number of instruction memory wait states pro-

grammed in DCR

nDW is the number of data memory wait states pro-

grammed in DCR

nLW is the number of remote wait states due to a BCP

local data memory access

nRW is the number of CPU wait states due to a remote

access

MAX(AB) means take the greater value of A or B

The following table is an example of the format used for the

timing specifications In this example tW-RD indicates a

pulse width specification for the output pin READ The ID

for locating the parameter in the timing waveforms is 10

The formula for this specification involves data and instruc-

tion memory wait states and the CPU clock period For the

case of 3 data memory wait states and 0 instruction memory

wait states and a CPU clock period of 50 ns the READ low

minimum pulse width would be calculated as

(MAX(30b1)a1)Ta(b10) e 4T b 10 e 190 ns

For the case of 1 data memory wait state and 3 instruction

memory wait states and a CPU clock period of 50 ns the

READ low minimum pulse width would be calculated as

(MAX(13b1)a1)Ta(b10) e 3T b 10 e 140 ns

To calculate nLW the following two equations are needed

nLW (min) e 0

nLW (max) e MAX(nDW nIW–1)aData Memory Access Cy-

cle

Data Memory Access Cycle is normally 3 T-states if 4TR

0 and 4 T-states if 4TR e 1 Keep in mind that both

LOR and WAIT can extend nLW

Symbol

Parameter

Formula

Min

Max

Units

tW-RD

Read Low

(MAX(nDW nIWb1)a1)Tab10

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