DP8344 datasheet(43/184 Pages) NSC

43 / 184 page

20 CPU Description (Continued)

223 Interrupts

The DP8344B has two external and four internal interrupt

sources The external interrupt sources are the Non-Maska-

ble Interrupt pin NMI and the Bi-directional Interrupt Re-

quest pin BIRQ

External

A non-maskable interrupt is detected by the CPU when a

falling edge is detected at the NMI pin The interrupt is auto-

matically cleared internally when the CPU recognizes the

interrupt

BIRQ can function as both an interrupt into the DP8344B

and as an output which can be used to interrupt other devic-

es BIRQ is configured as an input or output according to

the state of BIC in the Auxiliary Control Register

ACR

BIRQ is an input if BIC is a zero and an output when BIC

is a one The reset state of BIC is a zero causing BIRQ to

be an input after the BCP is reset

BIRQ in the Condition

Code Register

CCR

is a read only bit which mirrors the

state of BIRQ regardless of whether BIRQ is configured as

an input or output This bit is updated at the beginning of T1

of each instruction

When BIRQ is configured as an input an interrupt will occur

if the pin is held low BIRQ must be held low until the inter-

rupt is recognized or the interrupt will not be processed Due

to the prioritizing of interrupts as described below BIRQ

may not be recognized by the CPU until higher priority inter-

rupts have been serviced BIRQ will be recognized after

higher priority interrupts have been processed The low

state on BIRQ should be removed after the CPU recognizes

the interrupt or the interrupt will be processed multiple

times

When BIRQ is configured as an output its state is controlled

by IM3 in the Interrupt Control Register

ICR

Changing

the state of this bit will change BIRQ at the beginning of T1

of the instruction following the write to IM3

Note that

BIRQ in

CCR

is also updated at the beginning of T1

Therefore there is a one instruction cycle delay from when

IM3 changes to when the new value of BIRQ is made

available in BIRQ

BIS in the Remote Interface Configu-

ration register

RIC

mirrors the state of

IM3

When

BIRQ is an output writing a one to BIS will change the

state of IME thus changing BIRQ and allowing a remote

processor to acknowledge an interrupt from the BCP Note

if the BCP code operates on IM3 at the same time that the

remote processor acknowledges the interrupt by writing a

one to BIS BIRQ will toggle and then assume the state of

IM3 resulting from the BCP code operation Therefore if

the designer chooses to operate on IM3 while waiting for

the remote processor to acknowledge a BIRQ interrupt the

designer should ensure that the remote processor is locked

out from accessing BIS during the operation on IM3

This can be accomplished by setting LOR in ACR

hav-

ing the BCP perform a data memory access to ensure that

any current remote accesses are complete operating an

IM3

and finally clearing LOR

BIRQ will change state

two T-states after the end of the write to BIS

Writing a

one to BIS will have no effect on IM3 when BIRQ is an

input Table 2-26 summarizes the relationship between

BIRQ and its associated register bits

TABLE 2-26 BIRQ Control Summary

(a) BIRQ is an Input ( BIC e 0) Remote Processor Controls the State of BIRQ

IM3

BIS

BIRQ

IM3 e 0

Active Interrupt to the BCP state of

Reflects the state of BIRQ

BIRQ controlled by the Remote

Processor

IM3 e 1

Masked Interrupt to the BCP state of

Reflects the state of BIRQ

BIRQ controlled by the Remote

Processor

(b) BIRQ is an Output ( BIC e 1) BCP Controls the State of BIRQ

IM3

BIS

BIRQ

IM3 e 0

State of IM3 e 0

Reflects the state of BIRQ e 0

IM3 e 1

State of IM3 e 1

Reflects the state of BIRQ e 1

BIS

IM3

BIS

BIRQ

Remote Processor writesa1to BIS

Toggles

IM3

State of IM3

Reflects the

state of BIRQ

DP8344 Datasheet(PDF) 43 Page - National Semiconductor (TI)

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