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DP8344 Datasheet(PDF) 92 Page - National Semiconductor (TI) |
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DP8344 Datasheet(HTML) 92 Page - National Semiconductor (TI) |
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92 / 184 page  40 Remote Interface and Arbitration System (RIAS) (Continued) TLF9336 – H3 (c) This timing diagram shows a remote access setting up in time for WR-PEND rising to latch in the proper value of CMD The only set of arrows shows the BCP sampling the second remote access’s CMD value when WR-PEND rises The value of CMD will not be sampled again The BCP will carry out the second remote access as it was intended TLF9336 – H4 (d) This timing diagram shows a remote access starting after a half T-state plus a hold time since WR-PEND rose The first set of arrows shows the BCP sampling the value of CMD when WR-PEND rises The second set of arrows shows the BCP recognizing that no remote access has started and the value of CMD will be sampled for the next remote access The third set of arrows shows the BCP sampling the correct value of CMD for the second remote access The BCP will carry out the second remote access as it was intended FIGURE 4-26 Rest Time for Latched Write Mode (Continued) 92 |
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