DP8344 datasheet(70/184 Pages) NSC

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40 Remote Interface and Arbitration System (RIAS) (Continued)

TLF9336 – 96

FIGURE 4-12 Minimum BCPRemote Processor Interface

The BCP Remote Arbitrator State Machine (RASM) must

know what hardware interfaces to the RP in order to time

the remote accesses correctly To accomplish this three

Interface Mode bits in RIC are used to define the hard-

ware interface These bits are the Latched Write bit LW

the Latched Read bit LR and the Fast Buffered Write bit

FBW

See

Figure 4-13

BIS

FBW

MS1

MS0

Interface Mode Bits

– 0 – - Buffered Read

– 1 – - Latched Read

0 – 0 - Slow Buffered Write

1 – 0 - Fast Buffered Write

X – 1 - Latched Write

FIGURE 4-13 Interface Mode Bits

All combinations of Remote Reads or Writes with buffers or

latches can be configured via the Interface Mode bits A

Buffered Read is accomplished by using a buffer for block D

and setting LR e 0 Conversely using a latch for block D

and setting LR e 1 configures the RASM for Latched

Reads Using buffers for blocks A B and C and setting

LW e 0 allows either a Slow or Fast Buffered Write Set-

ting FBW e 0 configures RASM for a Slow Buffered Write

and

FBW

1 designates a Fast Buffered Write A

Latched Write is accomplished by using latches for blocks

A B and C and setting LW e 1

414 Execution Control

The BCP can be started and stopped in two ways If the

BCP is not interfaced to another processor it can be started

by pulsing RESET low while both REM-RD and REM-WR

are low Execution then begins at location zero If there is a

Remote Processor interfaced to the BCP a write to RIC

which sets the start bit STRT high will begin execution at

the current PC location Writing a zero to STRT stops exe-

cution after the current instruction is completed A Single-

Step is accomplished by writing a one to the Single-Step bit

SS in RIC

This will execute the instruction at the current

PC increment the PC and then return to idle

SS returns

low after the single-stepped instruction has completed SS

is a write only bit and will always appear low when RIC is

read

Two pins (WAIT and LOCK) and one register bit

LOR

can also affect the BCP CPU or RIAS execution The WAIT

pin can be used to add wait states to a remote access

When WAIT must be asserted low to add wait states is de-

pendent on which remote access mode is being used The

information needed to calculate when WAIT must be assert-

ed to add wait states is contained within the individual de-

scriptions of the modes in the next section (42 RIAS Func-

tional Description)

DP8344 Datasheet(PDF) 70 Page - National Semiconductor (TI)

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