DP8344 datasheet(78/184 Pages) NSC

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40 Remote Interface and Arbitration System (RIAS) (Continued)

On the next clock the state machine will enter RSF and LCL

will return low The A bus (and AD bus if the access is to

data memory) remains in TRI-STATE for the first half

T-state of RSF After the first half of RSF the Re-

mote Processor is no longer using the buses and the BCP

CPU will be granted the buses if LCL-BREQ is asserted If a

local bus request is made a local bus grant will be given to

the Timing Control Unit If the preceding access was a read

of IMEM then HIB is switched and if the access was to the

high byte of IMEM then the PC is incremented If RAE

REM-RD is deasserted at this point the next clock will bring

RASM back to RSA where it will loop until another Remote

Access is initiated RSG is entered if RAE REM-RD is still

true RASM will loop in RSG until RAE REM-RD is no longer

active at which time the state machine will return to RSA

Figure 4-17 the BCP is executing the first of two Data

Memory reads when REM-RD goes low In response XACK

goes low waiting the Remote Processor At the end of the

first instruction although the BCP begins its second write by

taking ALE high the RASM now takes control of the bus

and deasserts LCL high at the end of T1 A one T-state

delay is built into this transfer to ensure that READ has been

deasserted high before the data bus is switched The Timing

Control Unit is now waited inserting remote access wait

states TWr as RASM takes over

The remote address is permitted one T-state to settle on the

BCP address bus before READ goes low XACK then re-

turns high one T-state plus the programmed Data Memory

wait state TWd later having satisfied the memory access

time READ returns high a half T-state later ensuring suffi-

cient hold time followed by LCL being reasserted low after

an additional half T-state transferring bus control back to

the BCP The Remote Processor responds to XACK return-

ing high by deasserting REM-RD high although by this time

the BCP is well into its own memory read

423 Slow Buffered Write

The timing for this mode is the same as the Buffered Read

mode The complete flow chart for the Slow Buffered Write

mode is shown in

Figure 4-18 Until a Remote Write is initiat-

ed (RAE REM-WR true) the state machine (RASM) loops

in state RSA1 If a Remote Write is initiated and LOR is set

high RASM will move to state RSA2 Likewise if a Remote

Write is initiated while the buses have been granted locally

(ie Local Bus Grant e 1) RASM will move to state RSA2

The state machine will loop in state RSA2 as long as LOR

is set high or the buses are granted locally If the BCP CPU

needs to access Data Memory while in either RSA state

(and LOCK is high) it can still do so A local access is re-

quested by the Timing Control Unit asserting the Local Bus

Request (LCL-BREQ) signal A local bus grant will be given

by RASM if the buses are not being used (as is the case in

the RSA state)

XACK is taken low as soon as RAE REM-WR is true re-

gardless of an ongoing local access RASM will move into

RSB on the next clock after RAE REM-WR is asserted and

there is no local bus request and LOR e 0 No further

local bus requests will be granted until the remote access is

complete and RASM returns to RSA If the BCP CPU initi-

ates a Data Memory access after RSA the Timing Control

Unit will be waited and the BCP CPU will remain in state TWr

until completion of the remote access Half a T-state after

entering RSB the A and AD buses go into TRI-STATE

On the next CPU-CLK RASM enters RSC and LCL is taken

high while XACK remains low The wait state counters iIW

and iDW are loaded in this state from IW1–0 and DW2–

0 respectively in DCR

The A and AD buses now remain

in TRI-STATE and the Access Phase begins If the Remote

Access is to IMEM and the high instruction byte flag is set

(ie HIB e 1) then IWR is asserted low in RSC The state

machine can move into one of several states depending on

the state of CMD and MS1–0

on the next clock XACK

remains low and LCL remains high in all the possible next

states If CMD is high the access is to RIC and the next

state will be RSD1 The path from AD to RIC opens in this

state Any remote access mode changes made by this write

will not take effect until one T-state after the completion of

the present write

The five other next states all have CMD low and depend on

the Memory Select bits If MS1–0 is 10 or 11 the state

machine will enter either RSD2 or RSD3 and the low or high

bytes of the Program Counter respectively will be written

MS1–0 equal to 00 designates a Data Memory access

and moves RASM into RSD4 WRITE will be asserted in this

state and A and AD continue to be tri-stated This allows the

Remote Processor to drive the Data Memory address and

data buses for the write Since DMEM is subject to wait

states RSD4 is looped upon until all the programmed data

memory wait states have been inserted

The last possible Memory Selection is Instruction Memory

MS1–0 e 01 The two possible next states for IMEM de-

pend on whether RASM is expecting the low byte or high

byte Instruction words are accessed low byte then high

byte and RASM powers up expecting the low Instruction

byte The internal flag that keeps track of the next expected

Instruction byte is called the High Instruction Byte flag (HIB)

If HIB is low the next state is RSD5 and the low instruction

byte is written into the holding register ILAT If HIB is high

the high instruction byte is moved to I15 – 8 and the value in

ILAT is moved to I7 – 0 At the same time IWR is asserted

low beginning the write to instruction memory An IMEM

access like a DMEM access is subject to wait states and

these states will be looped on until all programmed Instruc-

tion Memory wait states have been inserted

Note

Resetting the BCP will reset HIB (ie

HIB e 0) Writing 01 to the

Memory Select bits in RIC (ie

MS1–0 e 01 pointing to IMEM)

will also force HIB to zero This way the instruction word boundary

can be reset without resetting the BCP

After all of the programmed wait states are inserted in the

RSD states more wait states may be added by asserting

WAIT low a half T-state before the end of the last pro-

grammed wait state If there are no programmed wait

states WAIT must be asserted low a half T-state before the

end of RSD to add wait states If WAIT remains low the

remote access is extended indefinitely All the RSD states

move to their corresponding RSE states on the CPU-CLK

after the programmed wait state conditions are met and

WAIT is high The RSE states are looped upon until RAE

REM-WR is deasserted LCL remains high in all RSE states

but XACK is taken back high to indicate that the remote

access can be terminated If XACK is connected to a Re-

mote Processor wait pin it can now terminate its write cycle

This state begins the Termination Phase The action speci-

fied in the conditional box is only executed while RAE REM-

WR is asserteda clock edge is not necessary

On the CPU-CLK after RAE REM-WR is deasserted RASM

enters RSF where LCL remains high and the BCP A and AD

buses are still in TRI-STATE The next CPU-CLK causes

RASM to move to RSA3 If the access was to IMEM then

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