DP8344 datasheet(75/184 Pages) NSC

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40 Remote Interface and Arbitration System (RIAS) (Continued)

Until a Remote Read is initiated (RAE REM-RD true) the

state machine (RASM) loops in state RSA1 If a Remote

Read is initiated and LOR is set high RASM will move to

state RSA2 Likewise if a Remote Read is initiated while the

buses have been granted locally (ie Local Bus Grant e 1)

RASM will move to state RSA2 The state machine will loop

in state RSA2 as long as LOR is set high or the buses are

granted locally If the BCP CPU needs to access Data Mem-

ory while in either RSA state (and LOCK is high) it can still

do so A local access is requested by the Timing Control

Unit asserting the Local Bus Request (LCL-BREQ) signal A

local bus grant will be given by RASM if the buses are not

being used (as is the case in RSA)

XACK is taken low as soon as RAE REM-RD is true re-

gardless of an ongoing local access If LOR is low RASM

will move into RSB on the next clock after RAE REM-RD is

asserted and there is no local bus request No further local

bus requests will be granted until RASM enters the Termina-

tion Phase If the BCP CPU initiates a Data Memory access

after RSA the Timing Control Unit will be waited and the

BCP CPU will remain in state TWr until the remote access

reaches the Termination Phase Half a T-state after entering

RSB the A bus (and AD bus if the access is to Data Memory)

goes into TRI-STATE

On the next clock RASM enters RSC and LCL is taken high

while XACK remains low The wait state counters iIW and

iDW are loaded in this state from IW1–0 and DW2–0

respectively in DCR

The A bus (and AD if the access is

to Data Memory) now remains TRI-STATE and the Access

Phase begins

The state machine can move into one of several states

depending on the state of CMD and MS1–0

on the next

clock XACK remains low and LCL remains high in all the

possible next states If CMD is high the access is to RIC

and the next state will be RSD1 Since the default state of

AD is RIC

it will not transition in this state The five other

next states all have CMD low and depend on the Memory

Select bits If MS1–0 is 10 or 11 the state machine will

enter either RSD2 or RSD3 and the low or high bytes of the

Program Counter respectively will be read

MS1–0

00 designates a Data Memory access and

moves RASM into RSD4 READ will be asserted low in this

state and A and AD continue to be tri-stated This allows the

Remote Processor to drive the Data Memory address for

the read Since DMEM is subject to wait states RSD4 is

looped upon until all the wait states have been inserted

The last possible Memory Selection is Instruction Memory

MS1–0 e 01 The two possible next states for the IMEM

access depend on if RASM is expecting the low byte or high

byte Instruction words are accessed low byte then high

byte and RASM powers up expecting the low Instruction

byte The internal flag that keeps track of the next expected

Instruction byte is called the High Instruction Byte flag (HIB)

If HIB is low the next state is RSD5 and the low instruction

byte is MUXed to the AD bus If HIB is high the high instruc-

tion byte is MUXed to AD and RSD6 is entered An IMEM

access like a DMEM access is subject to wait states and

these states will be looped on until all programmed instruc-

tion memory wait states have been inserted

Note

Resetting the BCP will reset HIB (ie

HIB e 0) Writing 01 to the

Memory Select bits in RIC (ie

MS1–0 e 01 pointing to IMEM)

will also force HIB to zero This way the instruction word boundary

can be reset without resetting the BCP

After all of the programmed wait states are inserted in the

RSD states more wait states may be added by asserting

WAIT low a half T-state before the end of the last pro-

grammed wait state If there are no programmed wait states

WAIT must be asserted low a half T-state before the end of

RSD to add wait states If WAIT remains low the remote

access is extended indefinitely All the RSD states move to

their corresponding RSE states on the CPU-CLK after the

programmed wait state conditions are met and WAIT is

high LCL remains high in all RSE states and A remains in

TRI-STATE (and AD if the access is to Data Memory)

XACK returns high in this state indicating that data is valid

so that it can be externally latched The action specific to

each RSD state remains in effect during the first half of the

RSE cycle (ie READ is asserted in the first half of RSE4)

This half T-state of hold time is provided to guarantee data

is latched when XACK goes high This state begins the Ter-

mination Phase

DP8344 Datasheet(PDF) 75 Page - National Semiconductor (TI)

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