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DP8344 Datasheet(PDF) 99 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP8344
Description  Biphase Communications Processor?좦CP
PDF  184 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8344 Datasheet(HTML) 99 Page - National Semiconductor (TI)

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50 Device Specifications (Continued)
TABLE 5-3 Data Memory Read Timing (Note 1)
Symbol
ID
Parameter
Formula
Min
Max
Units
tW-ALE
1
ALE High
(nRWa1)Tab10
12
ns
tPD-AAD-ALE
2
A AD (Data Address) Valid to ALE Falling
Tab22
ns
tPD-ALE-AD
3
ALE Falling to AD (Data Address) Invalid
TLab2ns
tH-RD-DATA
4
Data Valid after READ Rising
0
ns
tAZ-RD-AD
5
READ Falling to AD Disabled ( 4TR e0)
20
ns
tAZ-AD-RD
6
AD Disabled before READ Falling ( 4TR e1)
THab20
ns
tSU-RD-DATA
7
READ Falling to AD (Data) Setup ( 4TR e0)
(MAX(nDW nIWb1)a1)Tab22
ns
tSU-RD-DATA
8
READ Falling to AD (Data) Setup ( 4TR e1)
(MAX(nDWb1nIWb1)a1)TaTLab21
ns
tZA-RD-AD
9
READ Rising to AD Enabled
THab2ns
tPD-AAD-RD
10
A AD (Data Address) Valid before READ Falling
TaTLab27
ns
( 4TR e0)
tPD-AAD-RD
11
A AD (Data Address) Valid before READ Falling
2Tab27
ns
( 4TR e1)
tW-RD
12
READ Low ( 4TR e0)
(MAX(nDW nIWb1)a1)Tab10
10
ns
tW-RD
13
READ Low ( 4TR e1)
(MAX(nDWb1nIWb1)a1)TaTLab10
10
ns
tACC-D
14
Data Memory Read Time ( 4TR )e0)
(MAX(nDW nIWb1)a2)TaTLab40
ns
tACC-D
15
Data Memory Read Time ( 4TR )e1)
(MAX(nDWb1nIWb1)a3)TaTLab40
ns
tSU-AD-DATA
16
AD Disabled to AD (Data) Setup ( 4TR e0)
(MAX(nDW nIWb1)a1)Tab33
ns
tSU-AD-DATA
17
AD Disabled to AD (Data) Setup ( 4TR e1)
(MAX(nDWb1nIWb1)a2)Tab33
ns
tPD-ALE-AAD
18
ALE Rising to A AD (Data Address) Valid
(nRW)Ta
24
ns
tPD-RD-A
19
READ Rising to A Invalid
THa
0ns
Note 1
All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results
TLF9336 – 52
(a) Read Timing with ( 4TR e0)
TLF9336 – H7
(b) Read Timing with ( 4TR e1)
FIGURE 5-3 Data Memory Read Timing
99



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