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DP8344 Datasheet(PDF) 102 Page - National Semiconductor (TI) |
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DP8344 Datasheet(HTML) 102 Page - National Semiconductor (TI) |
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102 / 184 page ![]() 50 Device Specifications (Continued) TABLE 5-6 Clock Timing (Note 1) Symbol ID Parameter Formula Min Max Units tT-X1 1 X1 Period (Note 2) 50 500 ns tPD-X1-CO 2 X1 to CLK-OUT (Note 2) 37 ns tPD-CO-ICLKr 3 CLK-OUT Rising to ICLK Rising 15 ns tPD-CO-ICLKf 4 CLK-OUT Rising to ICLK Falling (Note 3) 15 ns tT-XT 5 X-TCLK Period (Note 4) 50 500 ns tW-X1HL 6 X1 High and Low time Pulse Widths (Note 5) 21 ns tW-XTHL 7 XTCLK High and Low Time Pulse Widths 15 ns Note 1 All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing specification may lead to invalid results Note 2 Measurement thresholds at 25V Note 3 The falling edge of ICLK occurs only after the next IA becomes valid The CLK-OUT cycle in which this occurs depends on the instruction being executed and the number of programmed instruction wait states Note 4 There is no relationship between X1 and X-TCLK X-TCLK is fully asynchronous Note 5 External loading on pin X2 equal to 15 pF See Figure 5-6b for affect of X2 loading in non-crystal applications (ie an external oscillator driving X1) TLF9336 – 55 TLF9336 – H8 FIGURE 5-6 Clock Timing 102 |
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