DP8344 datasheet(58/184 Pages) NSC

58 / 184 page

30 Transceiver (Continued)

form the 16-bit frame Additional fill bits may be inserted

between frames of a multi-frame transmission by loading

the fill bit register

FBR

with the one’s complement of the

number of fill bits to be transmitted A value of FF (hex)

corresponds to the addition of no extra fill bits At the con-

clusion of a message the transmitter will return to the idle

state after transmitting the 3 fill bits of the last frame (no

additional fill bits will be transmitted)

As shown in Table 3-1 the transceiver can operate in 2

different 5250 modes designated ‘‘promiscuous’’ and ‘‘non-

promiscuous’’ The transmitter operates in the same man-

ner in both modes

In the promiscuous mode the receiver passes all received

data to the CPU via the FIFO regardless of the station ad-

dress The CPU must determine which station is being ad-

dressed by reading TSR 2–0

before reading RTR

In the non-promiscuous mode the station address field

(B4 – B6) of the first frame must match the 3 least significant

bits of the Auxiliary Transceiver Register

ATR 2–0

be-

fore the receiver will pass the data on to the CPU If no

match is detected in the first frame of a message and if no

errors were found on that frame the receiver will reset to

idle looking for a valid start sequence If an address match

is detected in the first frame of a message the received

data is passed on to the CPU For the remainder of the

message all received frames are decoded in the same man-

ner as the promiscuous mode

To maintain maximum flexibility the receiver logic does not

interpret the station address or command fields in determin-

ing the end of a 5250 message The message typically ends

with no further line transitions after the third fill bit of the last

frame This end of message must be distinguished from a

loss of synchronization between frames of a multi-byte

transmission condition by looking for line activity some time

after the loss of synchronization occurs When the loss of

synchronization occurs during fill bit reception the receiver

monitors the Line Active flag

for up to 11 biphase bit

times (11 ms at the 1 MHz data rate) If LA goes inactive at

any point during this period the receiver returns to the idle

state de-asserting RA and asserting LTA

If however

LA is still asserted at the end of this window the receiver

interprets this as a real loss of synchronization and flags the

LMBT error condition to the CPU (See Receiver Errors in

this section)

In the 5250 modes the Data-Error-or-Message-End DEME

flag is a decode of the 111 station address (the end of mes-

sage delimiter) and is valid only when DAV is asserted

This function allows the CPU to quickly determine when the

end of message has been received

The transmitter has the flexibility of holding TX-ACT active

at the end of a 5250 message thus reducing line reflections

and ringing during this critical time period The amount of

hold time is programmable from 0 ms to 155 ms in 500 ns

increments (assuming TCLK is 8 MHz) and is set by writing

the selected value to the upper 5-bits of the Auxiliary Trans-

ceiver Register

ATR 7–3

General Purpose 8-Bit Modes

As shown in Table 3-1 the transceiver can operate in 2

different 8-bit modes designated ‘‘promiscuous’’ and ‘‘non-

promiscuous’’ In the non-promiscuous mode the first frame

data byte (B2 – B9) must match the contents of ATR 7–0

before the receiver will load the FIFO and assert DAV

no match is made on the first frame and if no errors were

found on that frame the receiver will go back to idle looking

for a valid start sequence The address comparator logic is

not enabled in the promiscuous mode and therefore all re-

ceived frames are passed through the receive FIFO to the

CPU The transmitter operates in the same manner in both

modes

The serial bit positions relative to the parallel data loaded

into the transmit FIFO and presented to the CPU by the

receiver FIFO are shown in

Figure 3-11 To transmit a

frame the data byte is written to RTR

loading the trans-

mit FIFO where it propagates through to the last location to

be loaded into the encoder and formatted for transmission

Only OWP in TCR is loaded into the transmitter FIFO in

both protocol modes

TCR 2–0

are don’t cares B10 is

defined by a parity calculation on B1 – B9 odd if OWP is

high and even if OWP is low

When a frame is received the decoder loads the processed

data into the receive FIFO where it propagates through to

the last location and is mapped into

RTR

All bits are

exactly as received Reading the data is accomplished by

reading

RTR

TSR 2–0

are undefined in the 8-bit

modes

TLF9336 – 50

FIGURE 3-11 General Purpose 8-Bit Frame AssemblyDisassembly Procedure

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