DP8344 datasheet(16/184 Pages) NSC

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20 CPU Description (Continued)

Just as TF10 – 8 bits get pushed onto the transmitter FIFO

when a write to

RTR

occurs the Receiver FIFO bits

RF10 – 8

in the Transceiver Status Register

TSR

re-

flect the state of the top word of the receive FIFO

TSR

also contains flags that show Transmit FIFO Full

TFF

Transmitter Active TA Receiver Error RE Receiver Ac-

tive

and Data AVailable

DAV

These flags may be

polled to determine the state of the transceiver For in-

stance during a Receiver Active interrupt the BCP can que-

ry the DAV bit to determine whether data is ready in the

receiver FIFO yet

The Error Code Register

ECR

contains flags for receiver

errors As previously stated the SEC bit in TRC must be

set high to read this register Reading ECR or resetting

the transceiver with TRES will clear all the errors that are

present The receiver OVerFlow flag OVF is set when the

receiver attempts to add another word to the FIFO when it is

full If internally checked parity and parity transmitted with a

3270 message conflict then the PARity error bit

PAR

set high The Invalid Ending Sequence bit

IES

isset

when the ending sequence in a 3270 3299 or 8-bit mes-

sage is incorrect When the expected mid-bit transition in

the Manchester waveform does not occur a Loss of Mid-Bit

Transition occurs ( LMBT ) Finally if the transmitter is acti-

vated while the receiver is active the Receiver DISabled

while active flag

RDIS

will be set unless RPEN is as-

serted

The second register in Main A bank is called the Network

Command Flag register

NCF

and contains information

about the transceiver which is useful for polling the trans-

ceiver (during other tasks for example) to see if it needs

servicing These flags include bits to indicate Transmit FIFO

Empty TFE

Receive FIFO Full RFF

Line Active LA

and a Line Turn Around LTA

LTA indicates that a mes-

sage has been received without error and a valid ending

sequence has occurred These flags facilitate polling of the

transceiver section when transceiver interrupts are not

used Also included in this register is a bit called DEME

(Data ErrorMessage End) In 32703299 modes this bit

indicates a mismatch between received and locally generat-

ed byte parity In 5250 modes

DEME decodes an end of

message indicator (111 in the address field) Three other

bits Received Auto Response RAR

Acknowledge ACK

and Poll POLL are decoded from a received message (at

the output of the receive FIFO) and are valid only in 3270

3299 modes where response time is critical

Section 30 Transceiver provides comprehensive coverage

of this on-chip peripheral

2116 Condition CodesRemote Handshaking Register

The ALU condition codes are available in the Condition

Code Register CCR

The Z bit is set when a zero result

is generated by an arithmetic logical or shift instruction

Similarly

N indicates the Negative result of the same op-

erations An oVerflow condition from an arithmetic instruc-

tion sets the V bit in CCR

The Carry bit C indicates a

carry or borrow result from an arithmetic instruction See

Section 222 ALU for more information

The Condition Code Register

CCR

also contains BIRQ

a status bit which reflects the logic level of the bidirectional

interrupt input pin BIRQ Hence this pin can be used as a

general purpose inputoutput port as well as a bidirectional

interrupt request as defined by bits in ACR and ICR

Ifa

remote CPU is present and shares data memory (dual port

memory) with the BCP handshaking can be accomplished

by using the two status bits in CCR called RR and RW

which indicate Remote Read and Remote Write accesses

respectively

In ACR

a lock bit

LOR

is available to lock out all host

accesses When this bit is set all host accesses are dis-

abled Locking out remote accesses is often done during

interrupts to ensure quick response times

The Remote Interface Configuration register

RIC

isnot

available to the BCP internally The Remote Interface Refer-

ence section provides further detail on RIC and interfac-

ing a remote processor

2117 Index Registers

Four index registers called IW IX IY and IZ provide 16-bit

addressing for both data memory and instruction memory

Each of these index registers is actually a pair of 8-bit regis-

ters which are individually addressable just like any other

CPU register They occupy register addresses R12 through

R19 Thus the first two pointers IW and IX (comprising

R12 – R15) can be accessed with immediate mode instruc-

tions (which can access only R0 to R15) Refer to Section

2132 Addressing Modes to see how the index registers

are formed from R12 – R19

Accessing data memory requires the use of one of the four

index registers All such instructions allow you to specify

which pointer is to be used except the immediate-relative

moves MOVE rs IZan and MOVE IZan rd These in-

structions always use the IZ pointer Register indirect opera-

tions have options to alter the value of the index register

the options include pre-increment

post-increment

and

post-decrement

These options facilitate block moves

searches etc Refer to Section 213 Instruction Set for

more information about data moves

Since the BCP’s ALU is 8 bits wide all code that manipu-

lates the index registers must act on them eight bits at a

time

The index registers can also be used in register indirect

jumps (LJMP Ir ) useful in implementing relocatable code

Any one of the index registers can be specified to provide

the 16-bit instruction address for the indirect jump

2118 Stack Registers

The last two register addresses (R30R31) are dedicated to

provide access to the two on-chip stacksthe data stack

and the address stack The data stack is 8 bits wide and 16

words deep It is a Last In First Out (LIFO) type and provides

high speed storage for variables pointers etc The address

stack is 23 bits wide and 12 words deep providing twelve

levels of nesting of subroutines and interrupts It is also a

LIFO structure and stores processor status as well as return

addresses from CALL instructions TRAP instructions and

interrupts The seven bits of processor status consist of the

four ALU flags ( C

and Z ) the current bank

setting (two bits) and GIE

Stack pointers for both the on-chip stacks are provided in

R30 the Internal Stack Pointer register

ISP

The lower

four bits are the pointer for the data stack and the upper

four bits are the pointer for the address stack Both internal

stacks are circular For example if 16 bytes are written to

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