DP8344 datasheet(14/184 Pages) NSC

14 / 184 page

20 CPU Description (Continued)

Registers in the R0 – R11 address space are allocated in a

manner that minimizes the need to switch banks

Main A

CPU control and transceiver status

Alternate A

CPU and transceiver configuration

Main B

8 general purpose

Alternate B

4 transceiver access 4 general purpose

Most of the BCP’s instructions with register operand(s) can

access all 32 register locations Only instructions with an

immediate operand are limited to the first sixteen register

locations (R0 – R15) These instructions however still have

access to all registers required for transceiver operation

CPU status and control registers 12 general purpose regis-

ters and two of the index registers

The general purpose registers are used for the majority of

BCP operations There are 8 general purpose registers in

Main Bank B (R4 – R11) 4 in Alternate Bank B (R8 – R11)

and 8 more (R20 – R27) that are always accessible but are

outside the limited register range Since these registers are

internal to the BCP they can be accessed without data

memory wait states speeding up processing time The in-

dex registers may also be used as general purpose registers

if required

For those instructions that require two operands an accu-

mulator (R8 one in each bank) serves as the second oper-

and The result of such an operation is stored back in the

accumulator only if it is specified as the destination thus

allowing

three

operand

operations

such

xR20 See Section 213 Instruction Set for further ex-

planation

Most registers have a predetermined state following a reset

to the BCP Refer to Section 62 Register Set Reference for

a detailed summary

2111 Banked Registers

The CPU register set was designed to optimize CPU per-

formance in an environment which supports multiple tasks

Generally the most important and time critical of these tasks

will be maintaining the serial link (servicing the transceiver

section) which often requires real time processing of com-

mands and data Therefore all transceiver functions have

been mapped into special function registers which the CPU

can access quickly and easily Switching between this task

and other tasks has been facilitated by dedicating a register

bank (Alternate B) to transceiver functions Alternate Bank

B provides access to all transceiver status control and

data in addition to four general purpose registers for proto-

col related storage Main Bank B contains eight general pur-

pose registers for use by other tasks Having general pur-

pose registers in both B banks allows for quick context

switching and also helps eliminate some of the overhead of

saving general purpose registers The main objective of this

banked register structure is to expedite servicing of the

transceiver as a background (interrupt driven) task allowing

the CPU to efficiently interleave that function with other

background and foreground operations

To facilitate using the transceiver in a polled fashion (in-

stead of using interrupts) many of the status flags neces-

sary to handshake with the transceiver are built into the

conditional jump instructions with others available in the

Main A bank (normally active) so that Alternate Bank B does

not have to be switched in to poll the transceiver Timer and

BIRQ tasks may also be run using polling techniques to

Main A bank

In general the registers have been arranged within the

banks so as to minimize the need to switch banks The pow-

er-up state is Alternate bank A Alternate bank B allowing

access to configuration registers Again the banks switch

by using the EXX instruction which explicitly specifies which

bank is active (Main or Alternate) for each register group (A

and B) The EXX instruction allows selecting any of four

possible bank settings with a single two T-state instruction

This instruction also has the option of enabling or disabling

the maskable interrupts

The contents of the special function registers can be divid-

ed into several groups for general discussiontimingcon-

trol interrupt control the transceiver the condition codes

the index registers the timer the stacks and remote inter-

face

2112 TimingControl Registers

The BCP provides a means to configure its external timing

through setting bits in the Device Control Register

DCR

and the Auxiliary Control Register

ACR

One of the first

configuration registers to be initialized on power-upreset is

DCR

which defines the hardware environment in which

the BCP is functioning Specifically

DCR

controls the

clock select logic for both the CPU and transceiver in addi-

tion to the number of wait states to be used for instruction

and data memory accesses

The BCP allows either one clock source operation for the

CPU and the transceiver from the on-chip oscillator or an

independent clock source can run the transceiver from the

eXternal Transceiver CLocK input X-TCLK The Transceiv-

er Clock Select bits

TCS10

select the clock source for

the transceiver which is either the on-chip Oscillator CLocK

OCLK or X-TCLK Options for selecting divisions of the on-

chip oscillator frequency are also provided (see the descrip-

tion of DCR in Section 62 Register Set Reference The

CPU Clock Select bit

CCS

allows the CPU to run at the

OCLK frequency or at half that speed The clock output at

the pin CLK-OUT however is never divided and always re-

flects the crystal frequency OCLK The frequency selected

for the transceiver (referred to as TCLK) should always be

eight times the desired serial data rate The frequency se-

lected for the CPU defines the length of each T-state (eg

20 MHz implies 50 ns T-states)

There are two independent fields for defining wait states

one for instruction memory access (nIW) and one for data

memory access (nDW) These fields specify to the BCP how

many wait states to insert to meet the access time require-

ments of both memory systems The Instruction memory

Wait-state select bits

IW10

and the Data memory Wait-

state select bits

DW2–0

control the number of inserted

wait states for instruction and data memory respectively

After a reset the maximum number of wait states are set in

DCR

nIW e 3 T-states and nDW e 7 T-states Wait-

states are discussed in more detail in Section 222 Timing

For a complete discussion on choosing your memory and

determining the number of wait states required please refer

to the application note

Choosing Your RAM for the Biphase

Communication Processor

DP8344 Datasheet(PDF) 14 Page - National Semiconductor (TI)

DP8344 Datasheet(HTML) 14 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL