DP8344 datasheet(53/184 Pages) NSC

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30 Transceiver (Continued)

TLF9336 – 45

FIGURE 3-7 Transmitter Output

322 Receiver

The receiver accepts a serial biphase-encoded bit stream

strips off the framing information checks for errors and re-

formats the data for parallel transfer to the CPU The block

diagram in

Figure 3-6 depicts the data flow from the serial

input(s) to the FIFO’s parallel outputs Note that the FIFO

outputs are multiplexed with the Error Code Register ECR

outputs

The receiver and transmitter share the same TCLK though

in the receiver this clock is used only to establish the sam-

pling rate for the incoming biphase encoded data All control

timing is derived from a clock signal extracted from this

data Several status flags and interrupts are made available

to the CPU to handle the asynchronous nature of the incom-

ing data stream See

Figure 3-8 for the timing relationships

of these flags and interrupts relative to the incoming data

The input source to the decoder can be either the on-chip

analog line receiver the DATA-IN input or the output of the

transmitter (for on-chip loopback operation) Two bits the

Select Line Receiver SLR and Loopback LOOP

control

this selection For interfacing to the on-chip analog line re-

ceiver see Section 3251 3270 Line Interface An example

of an external comparator circuit for interfacing to twinax

cable in 5250 environments is contained in Section 3252

5250 Line Interface The selected serial data input can be

inverted via the Receiver Invert RIN control bit

The receiver continually monitors the line sampling at a fre-

quency equal to eight times the expected data rate The

Line Active flag LA is asserted whenever an input tran-

sition is detected and will remain asserted as long as anoth-

er input transition is detected within 16 TCLK cycles If an-

other transition is not detected in this time frame

LA will

be de-asserted The propagation delay from the occurrence

of the edge to LA being set is approximately 1 transceiver

clock cycle This function is independent of the mode of

operation of the transceiver LA will continue to respond to

input signal transitions even if the transmitter is activated

and the receiver disabled

If the receiver is not disabled by the transmitter or by assert-

ing TRES

the decoder will adjust its internal timing to the

incoming transitions attempting to synchronize to valid bi-

phase-encoded data When synchronization occurs the bi-

phase clock will be extracted and the serial NRZ (Non-Re-

turn to Zero) data will be analyzed for a valid start se-

quence see

Figure 3-2(b) The minimum number of line

quiesce bits required by the receiver logic is selectable via

the Receiver Line Quiesce RLQ control bit If this bit is set

high (the power-up condition) three line quiesce bits are

required if set low only two are needed Once the start

sequence has been recognized the receiver asserts the

Receiver Active flag RA and enables the error detection

circuitry The propagation delay from the occurrence of the

mid-bit edge of the sync bit in the starting sequence to RA

being set is approximately 3 transceiver clock cycles

The NRZ serial bit stream is now clocked into a serial to

parallel shift register and analyzed according to the expect-

ed data pattern as defined by the protocol If no errors are

detected by the word parity bit the parallel data (up to a

total of 11-bits depending on the protocol) is passed to the

first location of the FIFO It then propagates asynchronously

to the last location in approximately 40 ns at which time the

Data Available flag DAV is asserted indicating to the CPU

that valid data is available in the FIFO The propagation

delay from the occurrence of the mid-bit edge of the parity

bit of the frame to DAV being set is approximately 5 trans-

ceiver clock cycles

Of the possible 11-bits in the last location of the FIFO 8-bits

(data byte) are mapped into RTR and the remaining bits

(if any) are mapped into the Transceiver Status Register

TSR 2–0

The CPU accesses the data byte by reading

RTR

and the 5250 address field or 3270 control bits by

reading

TSR

When reading the FIFO it is important to

note that TSR must be read before RTR

since reading

RTR

advances the FIFO Once DAV has been recog-

nized as set by the CPU the data can be read by any in-

struction with

RTR as the source All instructions with

RTR as the source (except BIT CMP JRMK JMP reg-

DP8344 Datasheet(PDF) 53 Page - National Semiconductor (TI)

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