DP8344 datasheet(30/184 Pages) NSC

30 / 184 page

20 CPU Description (Continued)

CCS as shown in

Figure 2-13 The switch occurs on the

falling edge of X1 when CPU-CLK is low CPU-CLK can be

changed back to OCLK2 by writing a one to CCS

The

point at which CPU-CLK changes depends on whether

there has been an odd or even number of T-states since

CCS was set low The change would require a maximum

of two T-states and a minimum of one T-state following the

end of the instruction that writes to CCS

The CPU is a RISC processor with a limited number of in-

structions which execute in a short period of time The maxi-

mum instruction cycle time is four T-states and the minimum

is two T-states Six types of instruction timing are used in

the CPU two T-state three T-state program control three

T-state data memory access four T-state read data memory

access four T-state program control and four T-state two

word program control The first T-state of each instruction

is T1 and the last T-state is T2 Intermediate T-states re-

quired to complete the instruction are referred to as TX

The instruction clock output ICLK defines the instruction

boundaries ICLK rises at the beginning of each instruction

and falls one-half T-state after the next address is generat-

ed on the instruction address bus IA Thus ICLK indicates

the start of each instruction and when the next instruction

address is valid

TLF9336 – D5

FIGURE 2-12 CPU-CLK Synchronization with X1

TLF9336 – D6

FIGURE 2-13 Changing from OCLK2 to OCLK

DP8344 Datasheet(PDF) 30 Page - National Semiconductor (TI)