DP8344 datasheet(64/184 Pages) NSC

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40 Remote Interface and Arbitration System (RIAS) (Continued)

arbitration logic determines that the BCP is not using data

memory LCL rises relinquishing control of the address and

data buses to the RP The remote access can be delayed at

most one BCP instruction (providing LOR is not set high)

If the CPU is executing a string of data memory accesses

RIAS has an opportunity to break in at the completion of

every instruction The time period between REM-RD or

REM-WR being asserted (with RAE low) and LCL rising is

called the Arbitration Phase It is a minimum of one T-state

but can be increased if the BCP CPU is accessing Data

Memory (local access) or if the BCP has set the Lock Out

Remote bit LOR

The CMD pin is internally latched on the first falling edge of

the CPU-CLK after a remote access has been initiated by

asserting RAE low along with asserting REM-RD or

REM-WR low If the remote interface is asynchronous the

CMD signal must be valid simultaneously or before RAE is

asserted low along with REM-RD or REM-WR being assert-

ed low The value of CMD is only sampled once during each

remote access and will remain in effect for the duration of

the remote access

After the Arbitration Phase has ended the Access Phase

begins Either Data Memory Instruction Memory the Pro-

gram Counter or

RIC

is read or written in this phase

Either INT-READ or INT-WRITE will fall one T-state after

LCL rises These two signals provide the timing for the dif-

ferent types of accesses INT-READ times the transitions on

the AD bus for Remote Reads and forms the external READ

line INT-WRITE clocks data into the PC and

RIC

and

forms the IWR and WRITE lines INT-READ and INT-WRITE

rise with XACK or shortly after

The duration of the Access Phase depends on the type of

memory being accessed Data Memory and Instruction

Memory accesses are subject to any programmed wait

states and all remote accesses are waited by asserting

WAIT low The minimum time in the Access Phase is 2

T-states

The rising edge of XACK indicates the Access Phase has

ended and the Termination Phase has begun If the RP was

doing a read operation this edge indicates that valid data is

available to the RP During the Termination Phase the BCP

is regaining control of the buses LCL falls one T-state after

XACK and since the RP is no longer being waited it can

deassert REM-RD or REM-WR The duration of this phase

is a minimum of one T-state but can be extended depend-

ing on the interface mode chosen in RIC

412 Access Types

There are four types of accesses an RP can make of the

BCP

Remote Interface Control Register RIC

Data Memory (DMEM)

Program Counter (PC)

Instruction Memory (IMEM)

An access of RIC is accomplished by asserting RAE and

REM-RD or REM-WR with the CMD pin asserted high The

Remote

Interface

Configuration

accessed

through the AD bus as shown in

Figure 4-4(c) A read or

write of RIC can take place while the BCP CPU is execut-

ing instructions Timing for this access is shown in

Figures

4-4(a) and (b) Note that in the Remote Read Figure 4-4(a)

AD does not transition This is because the contents of

RIC

are active on the bus by default The AD bus is in

TRI-STATE during a Remote Write

Figure 4-4(b) while LCL

is high The byte being written to RIC is latched on the

rising edge of XACK and can be seen on AD after LCL falls

The Access Phase in this case is always two T-states (un-

less WAIT is low) because RIC is not subject to any pro-

grammed wait states

TLF9336 – 80

(a) Remote Read Timing (RAE e 0)

TLF9336 – 81

(b) Remote Write Timing (RAE e 0)

TLF9336 – 82

FIGURE 4-4 Generic RIC Access

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