DP8344 datasheet(49/184 Pages) NSC

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30 Transceiver (Continued)

even word parity on the previous 12 bits Following the pari-

ty bit 3 biphase ‘‘0’’ fill bits (B0 – B2) are transmitted Follow-

ing these required fill bits up to 240 additional fill bits can be

inserted between frames before the next sync bit and the

start of the next frame of a multi-byte message The bit rate

on the twinax line is 1 MHz

3114 General Purpose 8-Bit

The framing format of the general purpose 8-bit protocol is

shown in

Figure 3-5 for both single and multi-frame mes-

sages It is identical to that used by the National Semicon-

ductor DP8342 transmitter and DP8343 receiver chips

Each message begins with a starting sequence and ends

with an ending sequence as shown in

Figures 3-2(b) and

(B1) an 8-bit data byte (B2 – B9) (LSB first) and the last bit

of the frame (B10) representing even word parity on the

previous 9 bits For multiplexed applications the first frame

can be designated as an address frame with all 8 bits avail-

able for the logical address (See General Purpose 8-bit

Modes in this section)

32 TRANSCEIVER FUNCTIONAL DESCRIPTION

A block diagram of the transceiver revealing external inputs

and outputs and details of the CPU interface is shown in

Figure 3-6 The transmitter and receiver are largely indepen-

dent of each other sharing only the clock reset and proto-

col select signals The transceiver is mapped into the CPU

be polled In addition the CPUTransceiver interface can be

configured for an interrupt-driven environment (See Trans-

ceiver Interrupts in this section)

Both transmitter and receiver are reset by a common Trans-

ceiver Reset bit TRES allowing the CPU to independently

reset the transceiver at any time The Transceiver is also

reset whenever the CPU reset is asserted including the re-

quired power-up reset When

TRES

is asserted both

transmitter and receiver FIFO’s are emptied resulting in the

Transmit FIFO Empty flag TFE being asserted and the

Data Available flag DAV cleared Other flags cleared by

TRES are Transmit FIFO Full TFF and Transmitter Ac-

tive TA in the transmitter and Line Active LA

Receiver

Active RA Receiver Error RE Receive FIFO Full RFF

Data Error or Message End DEME

POLL

ACK

and

RAR command flags in the receiver When TRES is as-

serted external pin TX-ACT is cleared DATA-DLY goes to a

state equal to the complement of Transmitter INvert TIN in

TMR

and DATA-OUT goes into a state equal to the com-

plement of TIN exclusive or’ed with the Advance Transmit-

ter Active ATA in TCR

In other words when TRES is

asserted DATA-DLY e TIN

and DATA-OUT e TIN Z

ATA

When TRES is asserted under software control it

is necessary to wait at least one instruction after asserting

TRES before seeing the resulting reset state of the affect-

ed flags in the CPU The transmitter and receiver are

clocked by a common Transceiver Clock TCLK at a fre-

quency equal to eight times the required serial data rate

TCLK can either be obtained from the on-chip oscillator di-

vided by 1 2 or 4 or from an external clock applied to the

X-TCLK pin TCLK selection is controlled by two Transceiv-

er Clock Select bits

TCS 1 – 0 located in the Device Con-

trol Register

DCR

TCS 1 – 0 should only be changed

when the transceiver is inactive

Since the TCLK source can be asynchronous with respect

to the CPU clock the CPUTransceiver interface can be

asynchronous All flags from the Transceiver are therefore

latched at the start of all instructions and parallel data is

transferred through 3 word FIFOs in both the transmitter

and receiver

Protocol selection is controlled by three Protocol Select

bits

PS2–0 in the Transceiver Mode Register

TMR

(see Table 3-1) Enough flexibility is provided for the BCP to

operate in all required positions in the network It is not pos-

TLF9336 – 42

(a) 8-Bit Single-Byte Message

TLF9336 – 43

(b) 8-Bit Multi-Byte Message

FIGURE 3-5 General Purpose 8-Bit Protocol Framing Format

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