DP8344 datasheet(55/184 Pages) NSC

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30 Transceiver (Continued)

323 Transceiver Interrupts

The transceiver has access to 3 CPU interrupt vectors one

each for the transmitter and receiver and a third the Line

Turn-Around interrupt providing a fast turn around capability

between receiver and transmitter The receiver interrupt is

the CPU’s highest priority interrupt (excluding NMI) fol-

lowed by the transmitter and Line Turn-Around interrupts

respectively The three interrupt vector addresses and a full

description of the interrupts are given in Table 3-2

The receiver interrupt is user-selectable from 4 possible

sources (only 3 used at present) by specifying a 2-bit field

the Receiver Interrupt Select bits RIS1-0 in the Interrupt

Control Register ICR

A full description is given in Table

3-3

The RFF a RE interrupt occurs only when the receive FIFO

is full (or an error is detected) If the number of frames in a

received message is not exactly divisible by 3 one or two

words could be left in the FIFO at the end of the message

since the CPU would receive no indication of the presence

of that data it is recommended that this interrupt be used

together with the line turn-around interrupt whose service

routine can include a test for whether any data is present in

the receive FIFO

For additional information concerning interrupts refer to

Sections 2113 Interrupt Control Registers and 223 In-

terrupts

324 Protocol Modes

32703299 Modes

As shown in Table 3-1 the transceiver can operate in 4

different 32703299 modes to accommodate applications

of the BCP in different positions in the network The 3270

mode is designed for use in a device or a controller which is

not in a multiplexed environment For a multiplexed network

the 3299 multiplexer and controller modes are designed for

each end of the controller to multiplexer connection the

3299 repeater mode being used for an in-line repeater situ-

ated between controller and multiplexer

For information on how parallel data loaded into the trans-

mit FIFO and unloaded from the receive FIFO maps into the

serial bit positions see

Figure 3-9

To transmit a frame

TCR 3–0

must first be set up with

the correct control information after which the data byte

can be written to

RTR

The resulting composite 12-bit

word is loaded into the transmit FIFO where it propagates

through to the last location to be loaded into the encoder

and formatted for transmission

When formatting a 3270 frame

TCR 2

controls whether

the transmitter is required to format a data frame or a com-

mand frame If TCR 2

is low the transmitter logic calcu-

TABLE 3-2 Transceiver Interrupts

Interrupt

Vector Address

Description

Receiver

000100

User selectable from 4 possible sources see Table 3-3

Transmitter

001000

Set when TFE asserted indicating that the transmit FIFO is empty cleared by

writing to RTR

Note

TRES causes TFE to be asserted

Line Turn-Around

001100

Set when a valid end sequence is detected cleared by writing to RTR

writing

a one to LTA or asserting TRES In 5250 modes interrupt is set when the

last fill bit has been received and no further input transitions are detected Will

not be set in 5250 or 8-bit non-promiscuous modes unless an address match

was received

The interrupt vector is obtained by concatenating

interrupt

IBR

0 0

vector address

vector

IBR with the vector address as shown

TABLE 3-3 Receiver Interrupts

Interrupt

RIS10

Description

RFFaRE

0 0

Set when RFF or RE asserted If activated by RFF indicating that the

receive FIFO is full interrupt is cleared by reading from RTR

If activated by

RE indicating that an error has been detected interrupt is cleared by reading

from ECR

DAVaRE

0 1

Set when DAV or RE asserted If activated by DAV

indicating that valid

data is present in the receive FIFO interrupt is cleared by reading from RTR

activated by RE indicating that an error has been detected interrupt is cleared

by reading from ECR

Not Used

1 0

Reserved for future product enhancement

1 1

Set when RA asserted indicating the receipt of a valid start sequence cleared

by reading ECR or RTR

All receiver interrupts can be cleared by asserting TRES

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