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DP8344 Datasheet(PDF) 103 Page - National Semiconductor (TI) |
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DP8344 Datasheet(HTML) 103 Page - National Semiconductor (TI) |
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103 / 184 page ![]() 50 Device Specifications (Continued) TABLE 5-7 Transceiver Timing (Note 1) Symbol ID Parameter Formula Min Max Units tPD-X1-TA 1 X1 Rising to TX-ACT RisingFalling 10 65 ns tPD-XTCLK-TA 2 X-TCLK Rising to TX-ACT RisingFalling 7 49 ns tPD-DODD-TA 3 DATA-OUT DATA-DLY Valid to TX-ACT Rising Ca 16 ns tW-DO-HB 4 DATA-OUT Half Bit Cell Width 4Cab10 10 ns tW-DO-FB 5 DATA-OUT Full Bit Cell Width 8Cab10 10 ns tPD-DO-DD 6 DATA-OUT FallingRising to DATA-DLY 2Cab10 10 ns RisingFalling (Note 3) Note 1 All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing specification may lead to invalid results Note 2 When ATA e1 TX-ACT is delayed by 4C and an additional line quiescent is generated resulting in 5 line quiescent pulses after the line interface logic The additional delay relative to a message with ATA e0 is 8C (one bit time) TLF9336 – 56 (a) Transmission Beginning Timing (Note 2) TLF9336 – 57 (b) Transmission Ending Timing FIGURE 5-7 Transceiver Timing 103 |
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