FDC37M607 datasheet(26/182 Pages) SMSC

26 / 182 page

DIGITAL INPUT REGISTER (DIR)

Address 3F7 READ ONLY

This register is read-only in all modes.

PC-AT Mode

BIT 0 - 6 UNDEFINED

The data bus outputs D0 - 6 will remain in a

high impedance state during a read of this

BIT 7 DSKCHG

This bit monitors the pin of the same name and

reflects the opposite value seen on the disk

cable or the value programmed in the Force

Disk

Change

(see

Configuration

PS/2 Mode

BIT 0 nHIGH DENS

This bit is low whenever the 500 Kbps or 1

Mbps data rates are selected, and high when

250 Kbps and 300 Kbps are selected.

BITS 1 - 2 DATA RATE SELECT

These bits control the data rate of the floppy

controller.

See Table 11 for the settings

corresponding to the individual data rates. The

data rate select bits are

unaffected by

software reset, and are set to 250 Kbps after a

hardware reset.

BITS 3 - 6 UNDEFINED

Always read as a logic "1"

BIT 7 DSKCHG

This bit monitors the pin of the same name

and reflects the opposite value seen on the

disk cable or the value programmed in the

Force

Disk

Change

(see

Configuration Register LD8:CRC1[1:0]).

DSK

CHG

RESET

COND.

N/A

DSK

CHG

DRATE

SEL1

DRATE

SEL0

nHIGH

nDENS

RESET

COND.

N/A

FDC37M607 Datasheet(PDF) 26 Page - SMSC Corporation

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