FDC37M607 datasheet(33/182 Pages) SMSC

33 / 182 page

PS/2 mode - (IDENT low, MFM high)

This mode supports the PS/2 models 50/60/80

configuration and register set. The DMA bit of

the DOR becomes a "don't care", (FINTR and

DRQ are always valid), TC and DENSEL

become active low.

Model 30 mode - (IDENT low, MFM low)

This

mode

supports

PS/2

Model

configuration and register set. The DMA enable

bit of ther DOR becomes valid (FINTR and DRQ

can be hi Z), TC is active high and DENSEL is

active low.

DMA TRANSFERS

DMA transfers are enabled with the Specify

command and are initiated by the FDC by

activating the FDRQ pin during a data transfer

command.

The FIFO is enabled directly by

asserting nDACK and addresses need not be

valid.

Note that if the DMA controller (i.e. 8237A) is

programmed to function in verify mode, a

pseudo read is performed by the FDC based

only on nDACK.

This mode is only available

when the FDC

has been configured into byte

mode (FIFO disabled) and is programmed to do

a read.

With the FIFO enabled, the FDC can

perform the above operation by using the new

Verify command; no DMA operation is needed.

The FDC37M60x supports two DMA transfer

modes for the FDC: Single Transfer and Burst

Transfer. In the case of the single transfer, the

DMA Req goes active at the start of the DMA

cycle, and the DMA Req is deasserted after the

nDACK. In the case of the burst transfer, the

Req is held active until the last transfer

(independent of nDACK). See timing diagrams

for more information.

Burst mode is enabled via Bit[1] of CRF0 in

Logical Device 0. Setting Bit[1]=0 enables burst

mode; the default is Bit[1]=1, for non-burst

mode.

CONTROLLER PHASES

For simplicity, command handling in the FDC

can be divided into three phases:

Command,

Execution, and Result. Each phase is described

in the following sections.

Command Phase

After a reset, the FDC enters the command

phase and is ready to accept a command from

the host. For each of the commands, a defined

set of command code bytes and parameter

bytes has to be written to the FDC before the

command phase is complete. (Please refer to

Table 19 for the command set descriptions.)

These bytes of data must be transferred in the

order prescribed.

Before writing to the FDC, the host must

examine the RQM and DIO bits of the Main

Status Register. RQM and DIO must be equal

to "1" and "0" respectively before command

bytes may be written. RQM is set false by the

FDC after each write cycle until the received

byte is processed. The FDC asserts RQM again

to request each parameter byte of the command

unless

illegal

command

condition

detected.

After the last parameter byte is

received, RQM remains "0" and the FDC

automatically enters the next phase as defined

by the command definition.

The FIFO is disabled during the command

phase to provide for the proper handling of the

"Invalid Command" condition.

FDC37M607 Datasheet(PDF) 33 Page - SMSC Corporation

FDC37M607 Datasheet(HTML) 33 Page - SMSC Corporation

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