FDC37M607 datasheet(84/182 Pages) SMSC

84 / 182 page

BIT 1 AUTOFD - AUTOFEED

This

bit

inverted

and

output

onto

the

nAUTOFD output. A logic “1” causes the printer

to generate a line feed after each line is printed.

A logic “0” means no autofeed.

BIT 2 nINIT - nINITIATE OUTPUT

This bit is output onto the nINIT output without

inversion.

BIT 3 SLCTIN - PRINTER SELECT INPUT

This bit is inverted and output onto the nSLCTIN

output. A logic “1” on this bit selects the printer;

a logic “0” means the printer is not selected.

BIT 4 IRQE - INTERRUPT REQUEST ENABLE

The interrupt request enable bit when set to a

high level may be used to enable interrupt

requests from the Parallel Port to the CPU. An

interrupt request is generated on the IRQ port by

a positive going nACK input. When the IRQE

bit is programmed low the IRQ is disabled.

BIT

PCD

PARALLEL

CONTROL

DIRECTION

Parallel Control Direction is not valid in printer

mode. In printer mode, the direction is always

out regardless of the state of this bit.

In bi-

directional, EPP or ECP mode, a logic 0 means

that the printer port is in output mode (write); a

logic 1 means that the printer port is in input

mode (read).

Bits 6 and 7 during a read are a low level, and

cannot be written.

EPP ADDRESS PORT

ADDRESS OFFSET = 03H

The EPP Address Port is located at an offset of

'03H' from the base address.

The address

During a WRITE operation, the contents of DB0-

DB7 are buffered (non inverting) and output onto

the PD0 - PD7 ports, the leading edge of nIOW

causes an EPP ADDRESS WRITE cycle to be

performed, the trailing edge of IOW latches the

data for the duration of the EPP write cycle.

During a READ operation, PD0 - PD7 ports are

read, the leading edge of IOR causes an EPP

ADDRESS READ cycle to be performed and the

data output to the host CPU, the deassertion of

ADDRSTB latches the PData for the duration of

the IOR cycle. This register is only available in

EPP mode.

EPP DATA PORT 0

ADDRESS OFFSET = 04H

The EPP Data Port 0 is located at an offset of

'04H' from the base address. The data register

is cleared at initialization by RESET. During a

WRITE operation, the contents of DB0-DB7 are

buffered (non inverting) and output onto the PD0

- PD7 ports, the leading edge of nIOW causes

an EPP DATA WRITE cycle to be performed,

the trailing edge of IOW latches the data for the

duration of the EPP write cycle. During a READ

operation, PD0 - PD7 ports are read, the leading

edge of IOR causes an EPP READ cycle to be

performed and the data output to the host CPU,

the deassertion of DATASTB latches the PData

for the duration of the IOR cycle. This register

is only available in EPP mode.

EPP DATA PORT 1

ADDRESS OFFSET = 05H

The EPP Data Port 1 is located at an offset of

'05H' from the base address.

Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

EPP DATA PORT 2

ADDRESS OFFSET = 06H

The EPP Data Port 2 is located at an offset of

'06H' from the base address.

Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

FDC37M607 Datasheet(PDF) 84 Page - SMSC Corporation

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