FDC37M607 datasheet(87/182 Pages) SMSC

87 / 182 page

logic "0" for an EPP write or a logic "1" for and

EPP read.

EPP 1.7 Write

The timing for a write operation (address or

data) is shown in timing diagram EPP 1.7 Write

Data or Address cycle.

IOCHRDY is driven

active low when nWAIT is active low during the

EPP cycle. This can be used to extend the cycle

time.

The write cycle can complete when

nWAIT is inactive high.

Write Sequence of Operation

The host sets PDIR bit in the control

This asserts

nWRITE.

The host selects an EPP register, places

data on the SData bus and drives nIOW

active.

The chip places address or data on PData

bus.

Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus contains valid

information, and the WRITE signal is valid.

nWAIT

asserted,

IOCHRDY

deasserted until the peripheral deasserts

nWAIT or a time-out occurs.

When the host deasserts nIOW the chip

deasserts nDATASTB or nADDRSTRB and

latches the data from the SData bus for the

PData bus.

Chip may modify nWRITE, PDIR and

nPDATA in preparation of the next cycle.

EPP 1.7 Read

The timing for a read operation (data) is shown

in timing diagram EPP 1.7 Read Data cycle.

IOCHRDY is driven active low when nWAIT is

active low during the EPP cycle. This can be

used to extend the cycle time. The read cycle

can complete when nWAIT is inactive high.

Read Sequence of Operation

The host sets PDIR bit in the control

This deasserts

nWRITE and tri-states the PData bus.

The host selects an EPP register and drives

nIOR active.

Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus is tri-stated, PDIR

is set and the nWRITE signal is valid.

nWAIT

asserted,

IOCHRDY

deasserted until the peripheral deasserts

nWAIT or a time-out occurs.

The Peripheral drives PData bus valid.

The Peripheral deasserts nWAIT, indicating

that PData is valid and the chip may begin

the termination phase of the cycle.

When the host deasserts nIOR the chip

deasserts nDATASTB or nADDRSTRB.

Peripheral tri-states the PData bus.

Chip

may modify nWRITE, PDIR

and

nPDATA in preparation of the next cycle.

FDC37M607 Datasheet(PDF) 87 Page - SMSC Corporation

FDC37M607 Datasheet(HTML) 87 Page - SMSC Corporation

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