FDC37M607 datasheet(71/182 Pages) SMSC

71 / 182 page

This bit controls the Data Terminal Ready

(nDTR) output. When bit 0 is set to a logic "1",

the nDTR output is forced to a logic "0". When

bit 0 is a logic "0", the nDTR output is forced to

a logic "1".

Bit 1

This bit controls the Request To Send (nRTS)

output.

Bit 1 affects the nRTS output in a

manner identical to that described above for bit

Bit 2

This bit controls the Output 1 (OUT1) bit. This

bit does not have an output pin and can only be

read or written by the CPU.

Bit 3

Output 2 (OUT2). This bit is used to enable an

UART interrupt. When OUT2 is a logic "0", the

serial port interrupt output is forced to a high

impedance state - disabled. When OUT2 is a

logic "1", the serial port interrupt outputs are

enabled.

Bit 4

This bit provides the loopback feature for

diagnostic testing of the Serial Port. When bit 4

is set to logic "1", the following occur:

The TXD is set to the Marking State (logic

"1").

The receiver Serial Input (RXD) is

disconnected.

The output of the Transmitter Shift Register

is "looped back" into the Receiver

Shift

All MODEM Control inputs (nCTS, nDSR,

nRI and nDCD) are disconnected.

The four MODEM Control outputs (nDTR,

nRTS, OUT1 and OUT2) are internally

connected to the four MODEM Control

inputs (nDSR, nCTS, RI, DCD).

The Modem Control output pins are forced

inactive high.

Data that is transmitted is immediately

received.

This feature allows the processor to verify the

transmit and receive data paths of the Serial

Port. In the diagnostic mode, the receiver and

the transmitter interrupts are fully operational.

The

MODEM

Control

Interrupts

are

also

operational but the interrupts' sources are now

the lower four bits of the MODEM Control

The interrupts are still controlled by the Interrupt

Enable Register.

Bits 5 through 7

These bits are permanently set to logic zero.

LINE STATUS REGISTER (LSR)

Address Offset = 5H, DLAB = X, READ/WRITE

Bit 0

Data Ready (DR).

It is set to a logic "1"

whenever a complete incoming character has

been received and transferred into the Receiver

Buffer Register or the FIFO. Bit 0 is reset to a

logic "0" by reading all of the data in the Receive

Buffer Register or the FIFO.

Bit 1

Overrun Error (OE). Bit 1 indicates that data in

the Receiver Buffer Register was not read before

the next

character was transferred into the

thereby

destroying

the

character. In FIFO mode, an overrunn error will

occur only when the FIFO is full and the next

character has been completely received in the

shift register, the character in the shift register is

overwritten but not transferred to the FIFO. The

OE indicator is set to a logic "1" immediately

upon detection of an overrun condition, and

reset whenever the Line Status Register is read.

FDC37M607 Datasheet(PDF) 71 Page - SMSC Corporation

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