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FDC37M607 Datasheet(PDF) 28 Page - SMSC Corporation |
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FDC37M607 Datasheet(HTML) 28 Page - SMSC Corporation |
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28 / 182 page  28 CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 for the appropriate values. BIT 2 - 7 RESERVED Should be set to a logical "0" PS/2 Model 30 Mode BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 for the appropriate values. BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. BIT 3 - 7 RESERVED Should be set to a logical "0" Table 12 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets. 7 6 5 4 3 2 1 0 DRATE SEL1 DRATE SEL0 RESET COND. N/A N/A N/A N/A N/A N/A 1 0 7 6 5 4 3 2 1 0 NOPREC DRATE SEL1 DRATE SEL0 RESET COND. N/A N/A N/A N/A N/A N/A 1 0 |
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