FDC37M607 datasheet(76/182 Pages) SMSC

76 / 182 page

DESIRED

BAUD RATE

DIVISOR USED TO

GENERATE 16X CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL*

CRxx:

BIT 7 OR 6

115200

0.16

230400

32770

0.16

460800

32769

0.16

*Note: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.

Table 34 - Reset Function Table

RESET CONTROL

RESET STATE

Interrupt Enable Register

RESET

All bits low

Interrupt Identification Reg.

RESET

Bit 0 is high; Bits 1 - 7 low

FIFO Control

RESET

All bits low

Line Control Reg.

RESET

All bits low

MODEM Control Reg.

RESET

All bits low

Line Status Reg.

RESET

All bits low except 5, 6 high

MODEM Status Reg.

RESET

Bits 0 - 3 low; Bits 4 - 7 input

TXD1, TXD2

RESET

High

INTRPT (RCVR errs)

RESET/Read LSR

Low

INTRPT (RCVR Data Ready)

RESET/Read RBR

Low

INTRPT (THRE)

RESET/ReadIIR/Write THR

Low

OUT2B

RESET

High

RTSB

RESET

High

DTRB

RESET

High

OUT1B

RESET

High

RCVR FIFO

RESET/

FCR1*FCR0/_FCR0

All Bits Low

XMIT FIFO

RESET/

FCR1*FCR0/_FCR0

All Bits Low

FDC37M607 Datasheet(PDF) 76 Page - SMSC Corporation

FDC37M607 Datasheet(HTML) 76 Page - SMSC Corporation

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