FDC37M607 datasheet(86/182 Pages) SMSC

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asserts (releases) IOCHRDY allowing

the host to complete the write cycle.

Peripheral asserts nWAIT, indicating to the

host that any hold time requirements have

been

satisfied

and

acknowledging

the

termination of the cycle.

Chip may modify nWRITE and nPDATA in

preparation for the next cycle.

EPP 1.9 Read

The timing for a read operation (data) is shown

in timing diagram EPP Read Data cycle.

IOCHRDY is driven active low at the start of

each EPP read and is released when it has been

determined that the read cycle can complete.

The read cycle can complete under the following

circumstances:

If the EPP bus is not ready (nWAIT is active

low) when nDATASTB goes active then the

read can complete when nWAIT goes

inactive high.

If the EPP bus is ready (nWAIT is inactive

high) then the chip must wait for it to go

active low before changing the state of

WRITE or before nDATASTB goes active.

The read can complete once nWAIT is

determined inactive.

Read Sequence of Operation

The host selects an EPP register and drives

nIOR active.

The chip drives IOCHRDY inactive (low).

If WAIT is not asserted, the chip must wait

until WAIT is asserted.

The chip tri-states the PData bus and

deasserts nWRITE.

Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus is tri-stated, PDIR

is set and the nWRITE signal is valid.

Peripheral drives PData bus valid.

Peripheral deasserts nWAIT, indicating that

PData is valid and the chip may begin the

termination phase of the cycle.

The chip latches the data from the

PData bus for the SData bus and

deasserts nDATASTB or nADDRSTRB.

This

marks

the

beginning

the

termination phase.

The chip drives the valid data onto the

SData

bus

and

asserts

(releases)

IOCHRDY

allowing

the

host

complete the read cycle.

Peripheral tri-states the PData bus and

asserts nWAIT, indicating to the host that

the PData bus is tri-stated.

10. Chip

may modify nWRITE, PDIR

and

nPDATA in preparation for the next cycle.

EPP 1.7 OPERATION

When the EPP 1.7 mode is selected in the

configuration register, the standard and bi-

directional modes are also available. If no EPP

Read, Write or Address cycle is currently

executing, then the PDx bus is in the standard or

bi-directional mode, and all output signals

(STROBE, AUTOFD, INIT) are as set by the

SPP Control Port and direction is controlled by

PCD of the Control port.

In EPP mode, the system timing is closely

coupled to the EPP timing. For this reason, a

watchdog timer is required to prevent system

lockup. The timer indicates if more than 10usec

have elapsed from the start of the EPP cycle

(nIOR or nIOW asserted) to the end of the cycle

nIOR or nIOW deasserted).

If a time-out

occurs, the current EPP cycle is aborted and the

time-out condition is indicated in Status bit 0.

Software Constraints

Before an EPP cycle is executed, the software

must ensure that the control register bits D0, D1

and D3 are set to zero. Also, bit D5 (PCD) is a

FDC37M607 Datasheet(PDF) 86 Page - SMSC Corporation

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