LTC6952 datasheet(30/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

Power Savings in SYSREF Generation Mode

In most applications, SYSREF requests are a rare oc-

currence. The LTC6952 provides modes to shut down

as much circuitry as possible while still maintaining the

correct timing relationship between SYSREF outputs and

clock outputs. Individual outputs may be put into a low

power mode while leaving the internal dividers running

by writing a “2” to the PDx bits, where x is the output of

interest. Additionally, putting the LTC6952 into SYSREF

generation mode (SRQMD=1) causes the part to draw a

significantly higher current than SRQMD=0. Therefore,

leave the SRQMD bit set to “0” until a SYSREF request is

required. When a SYSREF signal is needed, set SRQMD

to “1”, return the PDx bits to “0”, then wait at least 50µs

before issuing a SYSREF request. Put the SYSREF outputs

back into low power mode (PDx=2) and set SRQMD=0

when finished.

SERIAL PORT

The SPI-compatible serial port provides control and

monitoring functionality. A configurable status output

STAT gives additional instant monitoring.

Communication Sequence

The serial bus is composed of CS, SCLK, SDI, and SDO.

Data transfers to the part are accomplished by the se-

rial bus master device first taking CS low to enable the

LTC6952’s port. Input data applied on SDI is clocked on

the rising edge of SCLK, with all transfers MSB first. The

communication burst is terminated by the serial bus master

returning CS high. See Figure 16 for details.

Data is read from the part during a communication burst

using SDO. Readback may be multidrop (more than one

LTC6952 connected in parallel on the serial bus), as SDO

is three-stated (Hi-Z) when CS is high, or when data is

not being read from the part. If the LTC6952 is not used

in a multidrop configuration, or if the serial port master

is not capable of setting the SDO line level between read

sequences, it is recommended to attach a high-value resis-

tor of greater than 200k between SDO and GND to ensure

the line returns to a known level during Hi-Z states. See

Figure 17 for details.

MASTER–CS

MASTER–SCLK

tCSS

tCS

tCH

DATA

6952 F16

tCKL

tCKH

tCSS

tCSH

MASTER–SDI

MASTER–CS

MASTER–SCLK

LTC6952 –SDO

Hi-Z

6952 F17

8TH CLOCK

DATA

tDO

Figure 16. Serial Port Write Timing Diagram

Figure 17. Serial Port Read Timing Diagram

LTC6952 Datasheet(PDF) 30 Page - Analog Devices

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