LTC6952 datasheet(44/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Determining Output Digital Delay Values

The output digital delay is used to control phase relation-

ships between outputs. The minimum delay step is ½

of a period of the incoming VCO signal. For this design

example, the digital delay is used to place each device’s

SYSREF signal edges into a known phase relationship to its

corresponding device clock, optimized for the set-up (tS)

and hold time (th) requirements for that device. Assume

that the optimum SYSREF edge location for each device

occurs on the first falling clock edge before the desired

SYSREF valid rising clock edge. In other words, SYSREF

should change states ½ of a corresponding device clock

period before the SYSREF valid device clock edge. Refer

to Figure 29 for a visual example.

DEVICE CLOCK

SYSREF

6952 F29

SYSREF

TRANSITION

TARGET RANGE

DESIRED SYSREF

VALID CLOCK EDGE

Figure 29. SYSREF Edge Timing Example

In order to calculate each output’s digital delay value for

this design example, use the following procedure:

1. Delay all of the JESD204B device clocks by half of a

period of the slowest JESD204B device clock. This

delay setting is equal to the divide value of the slowest

device clock because a one code digital delay equals

half of a VCO cycle. Non-JESD204B clocks (such as

the FPGA management clock) are not included in

this calculation. This delay value defines the desired

SYSREF valid clock edge. In this example, the slowest

JESD204B clock is the FPGA device clock:

DDELSYSvalid = MFPGACLK = 32

DDELADC-CLK = DDELSYSvalid = 32

DDELDAC-CLK = DDELSYSvalid = 32

DDELFPGA-CLK = DDELSYSvalid = 32

2. For each device clock/SYSREF pair, subtract half a

device clock period from DDELSYSvalid to find the

SYSREF delay. This is equivalent to subtracting the

corresponding divide value of the device clock, i.e.

DDELADC-SYS = DDELSYSvalid – MADC-CLK

DDELADC-SYS = 32 – 8 = 24

DDELDAC-SYS = DDELSYSvalid – MDAC-CLK

DDELDAC-SYS = 32 – 1 = 31

DDELFPGA-SYS = DDELSYSvalid – MFPGA-CLK

DDELFPGA-SYS = 32 – 32 = 0

Table 23 summarizes the DDEL settings for all outputs.

Table 23. Output DDELx Settings for EZSync Standalone Design

Example

OUTPUT

PURPOSE

DDELx

OUT0

ADC0 SYSREF

OUT1

ADC0 CLK

OUT2

ADC1 SYSREF

OUT3

ADC1 CLK

OUT4

FPGA SYSREF

OUT5

FPGA DEV CLK

OUT6

FPGA MGMT CLK

OUT7

DAC0 SYSREF

OUT8

DAC0 CLK

OUT9

DAC1 SYSREF

OUT10

DAC1 CLK

Now that the output divider and delays have been deter-

mined, the LTC6952 can be programmed.

Status Register Programming

This example will use the STAT pin to alert the system

whenevertheLTC6952generatesafaultcondition.Program

x[5], x[3], x[1] = 1 to force the STAT pin high whenever

any of the LOCK, VCOOK, or REFOK flags asserts:

Reg01 = h2A

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