LTC6952 datasheet(43/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Selecting Loop Bandwidth

The next step in the algorithm is choosing the open loop

bandwidth (BW). The maximum BW should be at least

10x smaller than fPFD. Most data converter applications

will place the bandwidth at the optimal intersection of

VCO noise and in-band noise. Narrower bandwidths or

higher order loop filters can be used to lower spurious

power. For this example, the third-order loop filter shown

in Figure 24 will be used.

After inputting the external VCO phase noise and KVCO

characteristics, the LTC6952Wizard reports the thermal

noise optimized loop bandwidth is approximately 16kHz.

Loop Filter Component Selection

For the lowest in-band phase noise, ICP should be set to

the highest value possible that results in practical loop

filter component values. Therefore, ICP for our example is

chosen to be 11.2mA. The LTC6952Wizard uses Equation 9

to determine RZ:

RZ = 2 • π • 16k • 40/(11.2m • 5M)

RZ = 71.8Ω ≈ 71.5Ω

The LTC6952Wizard uses Equation 10 through 13 to

calculate CI, CP, C2, and R1:

CI = 4/(π • 16k • 71.5) = 1.11µF ≈ 1.2µF

CP = 1/(12 • π • 16k • 71.5) = 23.2nF ≈ 22nF

C2 = 1/(18 • π • 16k • 71.5) = 15.5nF ≈ 15nF

R1 = 71.5Ω

Note that resistors are rounded to standard ±1% values,

and capacitors are rounded to standard ±10% values.

Determining Output Modes

All outputs can be programmed as clocks (MODEx = 0),

SYSREFs (MODEx = 1 or 3), or SYNC/SRQ passthrough

outputs (MODEx = 2) using each output’s individual

MODEx bits as described in Table 13, Table 14, and Table 15.

Any output can also be programmed to ignore SYNC and

APPLICATIONS INFORMATION

SYSREF requests by setting that output’s correspond-

ing SRQENx bit to “0”. Noting that this design example

calls for pulsed SYSREFs (MODEx = 3) and that the

FPGA management clock should always be free running

(SRQENx = 0), Table 21 summarizes each output’s mode

settings.

Table 21. Output Mode Settings for EZSync Standalone Design

Example

OUTPUT

PURPOSE

SRQENx

MODEx

PDx

OUT0

ADC0 SYSREF

OUT1

ADC0 CLK

OUT2

ADC1 SYSREF

OUT3

ADC1 CLK

OUT4

FPGA SYSREF

OUT5

FPGA DEV CLK

OUT6

FPGA MGMT CLK

OUT7

DAC0 SYSREF

OUT8

DAC0 CLK

OUT9

DAC1 SYSREF

OUT10

DAC1 CLK

Determining Output Divider Values

Since the desired frequencies of each output are already

determined, the output divider values can be calculated

using Equation 7. The results are shown in Table 22.

Table 22. Output Divide Settings for EZSync Standalone Design

Example

OUTPUT

PURPOSE

Frequency

(MHz)

Divide Value

(Mx)

OUT0

ADC0 SYSREF

12.5

320

OUT1

ADC0 CLK

500

OUT2

ADC1 SYSREF

12.5

320

OUT3

ADC1 CLK

500

OUT4

FPGA SYSREF

12.5

320

OUT5

FPGA DEV CLK

125

OUT6

FPGA MGMT CLK

100

OUT7

DAC0 SYSREF

12.5

320

OUT8

DAC0 CLK

4000

OUT9

DAC1 SYSREF

12.5

320

OUT10

DAC1 CLK

4000

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