LTC6952 datasheet(45/80 Pages) AD

45 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Power and FILT Register Programming

For correct PLL operation, all internal blocks should be

enabled. Additionally, the REF and VCO input signals have

a sufficient slew rate and power to not need the FILT or

BST bits:

Reg02 = h00

Output Power-Down Programming

During initial setup and synchronization, all used outputs

and the SRQ circuitry should be set to full power. These

bits will be used later to place the IC in a lower power

mode while waiting for SYSREF requests:

Reg03 = h00

Reg04 = h00

Reg05 = h00

RAO and PARSYNC Programming

PARSYNC should be set to “0” since this example is not

a ParallelSync application. RAO should also be set to “0”

unless a highly accurate reference input to clock output

timing is required.

Lock Detect Programming

Next, determine the lock indicator window from fPFD.

From Table 4 we see that LKWIN = 0 with a tLWW of 3ns.

The LTC6952 will consider the loop “locked” as long as

the phase coincidence at the PFD is within ±3ns, or 108º

as calculated below.

phase = 360° • tLWW • fPFD

= 360º • 3n • 100M

≈ 108°

Larger values of COUNTS lead to more accurate and stable

lock indications at the expense of longer lock indication

times. A COUNTS value of 2048 will work for this applica-

tion. From Table 5, LKCT[1:0] = 3 for 2048 counts.

APPLICATIONS INFORMATION

R and N Divider Programming

The previously determined R and N divider values are 1

and 40, respectively. Using these values and the PARSYNC

and lock detector values, registers 6 through 9 can be

programmed:

Reg06 = h0C

Reg07 = h01

Reg08 = h00

Reg09 = h28

Charge Pump Function and Current Programming

Disable all the charge pump functions (CPMID, CPWIDE,

CPRST, CPUP, CPDN, and CPINV), allowing the loop to

lock. Using Table 6 with the previously selected ICP of

11.2mA gives CP[4:0] = h13.

SYNC and SYSREF Global Modes Programming

Bit EZMD controls whether the IC is an EZSync standalone/

controller (“0”) or follower (“1”). Since this example is an

EZSync standalone application, set bit EZMD to “0”. Bit

SRQMD determines if the part is in synchronization mode

(“0”) or SYSREF request mode (“1”). SYSCT programs

the number of pulses for any output in pulsed SYSREF

mode (# pulses = 2SYSCT, so SYSCT = 2 to achieve four

pulses for this example). Combining this information with

the previously determined charge pump controls, registers

h0A and h0B can be programmed:

Reg0A = h13

Reg0B = h04

Note that the SSRQ bit will remain “0” for now, but will be

used later during the synchronization and SYSREF request

procedures. Also, the EZS_SRQ± pins should be grounded

because the synchronization and SYSREF requests will be

accomplished through software control of the SSRQ bit.

Output Divider, Delay and Function Programming

Four registers for each output allow the outputs to be

configured independently of each other. The first register

controls the output divide ratio through two control words,

MPx and MDx, as described in Equation 1.

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