LTC6952 datasheet(57/80 Pages) AD

57 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

NDIV

VCO

RDIV

LF(s)

EZS_SRQ±

SYNC AND

SYSREF CTRL

M10

SYNC AND

SYSREF CTRL

M10

EZS_SRQ±

ADC1

SYSREF

CLK

SYSREF

CLK

ADC2

ADC3

DEV CLK

SYSREF

MGMT CLK

FPGA

SYSREF

CLK

ADC7

SYSREF

CLK

ADC6

ADC5

ADC4

LTC6952 #1

LTC6952 #2

NDIV

RDIV

REF±

SYNC

AND

SYSREF

CTRL

M10

LTC6953 REFERENCE

DISTRIBUTION

SSRQ

BIT

REF±

REF

OSC

ADC0

SYSREF

CLK

IN±

VCO±

VCO

LF(s)

VCO±

INPUT/OUTPUT TERMINATIONS AND

AC COUPLING CAPS NOT SHOWN

6952 F35

APPLICATIONS INFORMATION

Figure 35. Block Diagram for JESD204B ParallelSync with LTC6953 Reference Distribution Design Example

and LTC6952 #2). Figure 35 shows a block diagram of the

full system. Note that OUT0 of the reference LTC6953 is

driving the REF± inputs of LTC6952 #1 and OUT1 is driving

the EZS_SRQ± pins of LTC6952 #1. Likewise, OUT2 of the

reference LTC6953 is driving the REF± inputs of LTC6952

#2 and OUT3 is driving the EZS_SRQ± pins of LTC6952

#2. All outputs in this configuration are low RMS jitter

(~75fs ADC SNR Method).

Reference and VCO Assumptions

For this example, assume the available reference is a

245.76MHz sine wave oscillator with 8dBm output power,

and the VCOs are 2949.12MHz oscillators with a KVCO

of 15MHz/V, output power of 6dBm, and phase noise of

–112dBc/Hz at 10kHz.

fREF = 245.76MHz

fVCO = 2949.12MHz

KVCO = 15MHz/V

LTC6952 Datasheet(PDF) 57 Page - Analog Devices

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