LTC6952 datasheet(77/80 Pages) AD

77 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

TYPICAL APPLICATIONS

Generation of up to 125 ADC Clock/SYSREF Pairs Using a Three Stage Synchronization Architecture:

Synchronization Procedure and Measurement Results

Step 2: ParallelSYNC Multichip Clock Alignment

Step 3: SYSREF Alignment

Step 3: SYSREF Pulses

Step 1: Reference Alignment

Stage 3 LTC6952 Phase Noise vs

Stage 2 LTC6953 ADEL Setting

fOUT = 4GHz, Mx = 1

Initial Setup: Program LTC6952 and LTC6953 Registers

Settings Created from the LTC6952Wizard.

Step 1: Synchronize Stage 1&2 Reference Signals

A) EZSync: Toggle Stage 1 LTC6953 SSRQ Bit

B) OPT: Fine Alignment, Adjust Stage 2 ADEL Bits

Step 2: Synchronize Stage 3 Output Signals

A) Set Stage 1&2 LTC6953 SRQMD=1

B) ParallelSync: Toggle Stage 1 LTC6953 SSRQ Bit

Step 3: Send SYSREF Request

A) Power Up LTC6952 SYSREF Outputs

B) Set LTC6952 SRQMD=1

C) Send SYSREF: Toggle Stage 1 LTC6953 SSRQ Bit

Step 4: Optional Reduce Power

A) Power Down LTC6952 SYSREF Outputs

B) Set Stage 1&2 LTC6953 & LTC6952 SRQMD = 0

STAGE 2 ADEL ADJUSTMENTS

REF EDGE ALIGNED < ±5.5ps

(ADJUSTS FOR PART, CABLE & PCB MISMATCH)

5ns/DIV

LTC6952 #23

REF Input

LTC6952 #13

REF Input

6952 TAO4b

500ps/DIV

LTC6952 #13

OUT8: 4GHz

LTC6952 #23

OUT8: 4GHz

OUT1: 500MHz

6952 TAO4c

SYSREF Valid

Clock Edge

500ps/DIV

OUT0: SYSREF

12.5MHz

OUT1: CLOCK

500MHz

OUT7: SYSREF

12.5MHz

OUT8: CLOCK

4GHz

6952 TA04d

100ns/DIV

SYSREF

300mV/DIV

6952 TAO4e

RMS JITTER = 73fs

EQUIVALENT ADC SNR METHOD

STAGE 2 ADEL=0

STAGE 2 ADEL=31

STAGE 2 ADEL=63

OFFSET FREQUENCY (Hz)

10k

100k

10M 40M

–180

–170

–160

–150

–140

–130

–120

–110

–100

6952 TAO4f

LTC6952 Datasheet(PDF) 77 Page - Analog Devices

LTC6952 Datasheet(HTML) 77 Page - Analog Devices

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