LTC6952 datasheet(56/80 Pages) AD

56 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 34. Outputs after SYSREF Request for the EZSync Multi-Chip Design Example (SRQMD=1)

EZS_SRQ OR SSRQ BIT

CONTROLLER OUTPUTS

FOLLOWER OUTPUTS

6952 F31

FOLLOWER DRIVER

(OUT8)

SYSREQ PASSTHROUGH

(OUT9)

ADC DEVICE CLOCKS

(OUT1, 3, 5 AND 7)

ADC SYSREFs

(OUT0, 2, 4 AND 6)

DAC DEVICE CLOCKS

(OUT4, 6, 8 AND 10)

DAC SYSREFs

(OUT3, 5, 7 AND 9)

FPGA SYSREF

(OUT1)

FPGA DEVICE CLOCK

(OUT2)

4000MHz

FPGA MANAGEMENT CLOCK

(OUT10)

100MHz

4000MHz

125MHz

500MHz

JESD204B DESIGN EXAMPLE USING ParallelSync

This design example consists of a system of eight

JESD204B analog-to-digital converters (ADCs) and a

JESD204B compatible FPGA. All of the ADCs and the

FPGA require JESD204B subclass 1 device clocks and

SYSREFs, and the FPGA requires an extra management

clock. Additionally, the ADCs require low noise clocks of

less than 100fs total RMS jitter. This leads to a total of

19 separate signals to generate, with frequencies listed

below. For this example, the SYSREF frequencies for all

devices are the same and should output four pulses upon

a SYSREF request rising edge:

fADC-CLK = 294.912MHz

fFPGA-CLK = 147.456MHz

fFPGA-MGMT = 98.304MHz

fSYSREF = 9.216MHz

To determine which multi-chip configuration to use, we

utilize the flowchart in Figure 15. This example has nine

total JESD204B device clock/SYSREF pairs, eight of which

need to be less than 100fs total jitter. We also need one

additional non-low noise standalone clock for the FPGA.

Therefore:

TP = 9

LNP = 8

TS = 1

LNS = 0

Based on these inputs, Figure 15 suggests using the Paral-

lelSync Multi-Chip protocol with LTC6953 Reference Dis-

tribution topology shown in Figure 14, using one LTC6953

as the reference distribution chip (REF LTC6953) and two

LTC6952s in parallel to generate the clocks (LTC6952 #1

LTC6952 Datasheet(PDF) 56 Page - Analog Devices

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