LTC6952 datasheet(52/80 Pages) AD

52 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

3. Adjust for CONTROLLER vs FOLLOWER outputs.

Any CONTROLLER output that is synchronous with

the FOLLOWER must have the delay offset from

Equation 17 added to its DDEL value. FOLLOWER

outputs need no adjustment. For this example, the

ADC CLKs and SYSREFs come from the CONTROLLER:

DDELADC-CLK = DDELADC-CLK´ + DDELFS-OS

DDELADC-CLK = 32 + 14 = 46

DDELADC-SYS = DDELADC-SYS´ + DDELFS-OS

DDELADC-SYS = 24 + 14 = 38

DDELDAC-CLK = DDELDAC-CLK´ + 0 = 32

DDELDAC-SYS = DDELDAC-SYS´ + 0 = 31

DDELFPGA-CLK = DDELFPGA-CLK´ + 0 = 32

DDELFPGA-SYS = DDELFPGA-SYS´ + 0 = 0

Even though CONTROLLER OUT9 is only passing through

the SYNC/SRQ pulse, its digital delay should be set so

that its edges occur at the same time as the latest occur-

ring SYSREF in the overall system. This is to ensure that

future SYSREF requests are aligned properly. Note that

the delay offset from Equation 17 will need to be added

as well since it is located on the CONTROLLER part. The

latest occurring SYSREF is the DAC SYSREF, therefore:

DDELOUT9 = DDELDAC-SYS + DDELFS-OS

DDELOUT9 = 31 + 14 = 45

The follower-driver digital delay is set to 0 in this example:

DDELFD = DDELOUT8 = 0

Table 27 summarizes the DDEL settings for all outputs.

Table 27. Output DDELx Settings for EZSync Multi-Chip Design

Example

OUTPUT

PURPOSE

DDELx

OUT0

ADC0 SYSREF

OUT1

ADC0 CLK

OUT2

ADC1 SYSREF

OUT3

ADC1 CLK

OUT4

ADC2 SYSREF

OUT5

ADC2 CLK

OUT6

ADC3 SYSREF

OUT7

ADC3 CLK

OUT8

FOLLOWER VCO

OUT9

FOLLOWER EZS_SRQ

OUT10

FPGA MGMT CLK

OUT0

Unused

N/A

OUT1

FPGA SYSREF

OUT2

FPGA DEV CLK

OUT3

DAC0 SYSREF

OUT4

DAC0 CLK

OUT5

DAC1 SYSREF

OUT6

DAC1 CLK

OUT7

DAC2 SYSREF

OUT8

DAC2 CLK

OUT9

DAC3 SYSREF

OUT10

DAC3 CLK

Now that the output divider and delays have been deter-

mined, the ICs can be programmed.

Status Register Programming

This example will use the STAT pin to alert the system

whenever the LTC6952 generates a fault condition. For

the CONTROLLER, program x[5], x[3], x[1] = 1 to force

the STAT pin high whenever any of the LOCK, VCOOK, or

REFOK flags asserts:

CONTROLLER Reg01 = h2A

For the FOLLOWER, only the VCOOK flag is valid:

FOLLOWER Reg01 = h08

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