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LTC6952 Datasheet(PDF) 36 Page - Analog Devices

Part # LTC6952
Description  Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B Support
PDF  80 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC6952 Datasheet(HTML) 36 Page - Analog Devices

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LTC6952
36
6952f
For more information www.analog.com
Preliminary Technical Data
Advance Product Information Subject to Change
Rev PrA
OPERATION
STAT Output
The STAT output pin is configured with the x[6:0] bits and
INVSTAT of register h01. These bits are used to bit-wise
mask, or enable, the corresponding status flags of status
register h00, according to Equation 2 and shown sche-
matically in Figure 23. The result of this bit-wise Boolean
operation is then output on the STAT pin.
STAT = (OR (Reg00[6:0] AND Reg01[6:0]))
XOR INVSTAT
(2)
6952 F23
X[0]
REFOK
INVSTAT
STAT
TEMPO
X[1]
REFOK
X[2]
VCOOK
X[4]
LOCK
X[5]
LOCK
X[6]
UNLOCK
1
0
1
0
X[3]
VCOOK
Figure 23. STAT Simplified Schematic
For example, if the application requires STAT to go high
whenever the LOCK, VCOOK, or REFOK flags are set, then
x[4], x[2], and x[0] should be set to “1” and INVSTAT
should be set to “0”, giving a register value of h15.
The STAT pin may be transformed to a temperature mea-
surement diode with internal 300µA bias current by setting
bit TEMPO in register h05 to “1”. To get an approximate
die temperature, a single calibration point is needed first.
Measure the STAT pin voltage (VTEMPC) with the LTC6952
powered down (PDALL = 1) at a known temperature (TCAL).
Then the operating temperature may be calculated in a
desired application by measuring the STAT voltage again
(VTEMP) and using the following equation:
T = 665 × (VTEMPC – VTEMP) + TCAL
where T and TCAL are in ºC. Note that no external bias
current is required. Allow 50µs settling time after setting
TEMPO to “1”.
BLOCK POWER-DOWN CONTROL
The LTC6952’s power-down control bits are located in
register h02, described in Table 20. Different portions of
the device may be powered down independently. To power
down individual outputs, see Table 10. Care must be taken
with the LSB of this register, the POR (power-on-reset)
bit. When written to “1”, this bit forces a full reset of the
part’s digital circuitry to its power-up default state.



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