LTC6952 datasheet(66/80 Pages) AD

66 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Even if the reference input is a CMOS signal, it is still

required to be a high quality signal and is best routed on

50Ω transmission lines. Because CMOS drivers typically

are not capable of driving 50Ω, it is recommended to put

a resistor in series with the reference output before being

applied to the transmission line, and loaded with 50Ω to

GND as close to the LTC6952 as possible as shown in

Figure 25. See “REFERENCE SOURCE CONSIDERATIONS”

above. For production testing, the rise and fall times of

the EZS_SRQ and REF± signals are 1ns.

CMOS EZS_SRQ+

(EZS_SRQ– = GND)

DIFFERENTIAL

EZS_SRQ±

50%

REF±

6952 F39

tSH

VIH

tSS

CMOS EZS_SRQ+

(EZS_SRQ– = GND)

DIFFERENTIAL

EZS_SRQ±

50%

REF±

6952 F40

tSH

VIL

tSS

Figure 39. Rising EZS_SRQ to REF Timing Detail

Figure 40. Falling EZS_SRQ to REF Timing Detail

SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES

Care must be taken when creating a PCB layout to mini-

mize power supply decoupling and ground inductances.

All power supply V+ pins should be bypassed directly to

the ground plane using either a 0.01µF or a 0.1µF ceramic

capacitor as called out in the Pin Functions section as close

to the pin as possible. Multiple vias to the ground plane

should be used for all ground connections, including to

the power supply decoupling capacitors.

The package’s exposed pad is a ground connection, and

must be soldered directly to the PCB land. The PCB land

pattern should have multiple thermal vias to the ground

plane for both low ground inductance and also low thermal

resistance (see Figure 41 for an example). An example of

6952 F41

Figure 41. PCB Top Metal Layer Pin and Exposed

Ground Pad Design. Pin 41 is Signal Ground and

Connected Directly to the Exposed Pad Metal

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