LTC6952 datasheet(38/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

where KVCO is in Hz/V, ICP is in Amps, and RZ is in

Ohms. KVCO depends on the external VCO chosen for

the application. If the chosen VCO has a negative KVCO,

the CPINV bit must be set to “1” for correct opera-

tion. Use ICP = 11.2mA to lower in-band noise unless

component values force a lower setting.

4. Select loop filter components CI, CP, C2, and R1 based

on BW and RZ. Use the following equations to calculate

the remaining loop filter components.

CI = 4/(π • BW • RZ)

(10)

CP = 1/(12 • π • BW • RZ)

(11)

C2 = 1/(18 • π • BW • RZ)

(12)

R1 = RZ

(13)

DIGITAL AND ANALOG OUTPUT DELAYS

Synchronization allows the start times of each output

divider to be delayed by the value programmed into the

digital delay bits (DDELx), expressed in ½ VCO cycles.

Applications needing to calculate the delay in terms of time

can use Equation 14 where DDELx is DDEL0 to DDEL10:

tDDELx = DDELx/(2 • fVCO)

(14)

The analog delay blocks (ADELx) are useful in trimming

signal timing differences caused by non-ideal PCB routing.

This is effective for optimizing set-up and hold times for

SYSREFs versus device clocks in JESD204B applications.

Unlike digital delay, adding analog delay will adversely affect

the jitter performance. Add analog delay to the SYSREF path

whenever possible to minimize the impact on the device

clocks. For example, if the SYSREF signal in a SYSREF/

Clock pair is arriving at the destination device too late, it

is better to add one digital delay code to the device clock

and then add analog delay to the SYSREF, if necessary, to

bring it closer to the device clock.

The approximated analog delay time can be calculated in

picoseconds (ps) by Equation 15 (for ADELx < 32) while

adhering to the frequency limitations described in Table 11.

ADELx = 1 to 31

tADELx = [(11.25 • ADELx + 93.8)–2.5

+ (0.00285 • fOUTx)2.5]–0.4

(15)

ADELx = 32 to 63

tADELx = [(26 • ADELx - 517)–2.5

+ (0.00125 • fOUTx)2.5]–0.4

(16)

where fOUT is the output frequency in GHz. The

LTC6952Wizard may be used for analog delay calculation

and visualization.

REFERENCE INPUT

The LTC6952’s reference input buffer, shown in Figure 1,

provides a flexible interface to either differential or single-

ended frequency sources. The frequency range for the

reference input is from 1MHz to 500MHz. As discussed

in the Operation section, a high quality signal must be

applied to the REF± inputs as they provide the frequency

reference to the entire PLL. To achieve the part’s in-band

phase noise performance, apply a sine wave signal of at

least 6dBm into 50Ω, or a square wave of at least 0.5VP-P

with slew rate of at least 20V/µs. Figure 25 shows recom-

mended interfaces for different reference signal types.

VCO INPUT

The LTC6952’s VCO input buffer, shown in Figure 6, has a

frequency range of DC to 4.5GHz. The buffer has a partial

on-chip differential input termination of 250Ω, allowing

some flexibility for an external matching network if desired.

Figure 26 shows recommended interfaces for different

VCO input signal types.

LTC6952 Datasheet(PDF) 38 Page - Analog Devices

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