LTC6952 datasheet(68/80 Pages) AD

68 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Degradation of the SNR due to sample clock jitter only

occurs if the analog input signal is slewing. If the analog

input signal is stationary (DC) then it does not matter

when in time the sampling occurs. Additionally, a faster

slewing input signal yields a greater error (more noise)

than a slower slewing input signal.

Figure 43 demonstrates this effect. Note how much larger

the error term is with the fast slewing signal than with the

slow slewing signal. To maintain the data converter’s SNR

performance, digitization of high input frequency signals

requires a clock with much less jitter than applications

with lower frequency input signals.

6952 F43

∆V = VERROR(SLOW)

∆V = VERROR(FAST)

FAST

SINE WAVE

SLOW

SINE WAVE

Figure 43. Fast and Slow Sine Wave

Signals Sampled with a Jittery Clock

It is important to note that the frequency of the analog

input signal determines the sample clock’s jitter require-

ment. The actual sample clock frequency does not matter.

Many ADC applications that undersample high frequency

signals have especially challenging sample clock jitter

requirements.

The previous discussion was useful for gaining an intuitive

feel for the SNR degradation due to sampling clock jitter.

Quantitatively, the actual sample clock jitter requirement

for a given application is calculated as follows:

tJ(TOTAL) =

–SNR

2 •

π • fSIG

(22)

Where fSIG is the highest frequency signal to be digitized

expressed in Hz, SNRdB is the SNR requirement in decibels

and tJ(TOTAL) is the total RMS jitter in seconds. The total

jitter is the RMS sum of the ADC’s aperture jitter and the

sample clock jitter calculated as follows:

tJ(TOTAL) = tJ(CLK)

2 +t

J(ADC)

(23)

Alternatively, for a given total jitter, the attainable SNR is

calculated as follows:

SNRdB= –20log10 2• π• fSIG • tJ(TOTAL)

)

(24)

These calculations assume a full-scale sine wave input

signal. If the input signal is a complex, modulated signal

with a moderate crest factor, the peak slew rate of the

signal may be lower and the sample clock jitter require-

ment may be relaxed.

These calculations are also theoretical. They assume a

noiseless ADC with infinite resolution. All realistic ADCs

have both added noise and a resolution limit. The limita-

tions of the ADC must be accounted for to prevent over-

specifying the sampling clock.

Figure 44 plots the previous equations and provides a

simple, quick way to estimate the sampling clock jitter

requirement for a given input signal or the expected SNR

performance for a given sample clock jitter.

TOTAL CLOCK

JITTER (RMS)

10fs

20fs

50fs

100fs

200fs

500fs

1ps

FREQUENCY OF FULL-SCALE INPUT SIGNAL (GHz)

0.01

0.1

104

114

124

6952 F44

Figure 44. SNR vs Input Signal Frequency

vs Sample Clock Jitter

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