LTC6952 datasheet(25/80 Pages) AD

25 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

Table 15. Output Behavior in SYSREF Generation Mode

(SRQMD = 1)

SRQENx

MODEx

Output Behavior

Free Run, Ignore SYSREQ

1, 2, or 3

Muted, Ignore SYSREQ

Free Run, Ignore SYSREQ

Gated pulses: Run on SYSREQ High, Mute on

Low

SYSREQ Pass Through

Output 2SYSCT Pulses After SYSREQ Goes High

Table 16. Settings of EZMD and PARSYNC for Different Syn-

chronization Topologies

Control

Bit

EZSync

Standalone

(see Figure 10)

EZSync Multi-Chip

(see Figure 11 and Figure 12)

ParallelSync

Multi-Chip

(see Figure 13

and Figure 14)

CONTROLLER

FOLLOWER

PARSYNC

EZMD

Table 17. Parameters and Limitations of EZSync and ParallelSync (Two Stages Only)

EZSync

Standalone

(see Figure 10)

EZSync Multi-Chip

ParallelSync Multi-Chip

Pin Controlled Requests

(see Figure 11)

Request Passthough

(see Figure 12)

General

Reference

Distribution

(see Figure 13)

LTC6952

Reference

Distribution

(see Figure 14)

Controller

Follower

Controller

Follower

RMS Jittera

~75fs

~105fs

~75fs

~105fs

~75fs

Possible Number of Followers (Nfol)

1 to 11

1 to 5

Possible Number of Parallel Parts

(Npar)

Unlimitedb

1 to 5

Total Number of Outputs

11 - Nfol

11 · Nfol

11 – 2Nfol

11 · Nfol

11 · Npar

Maximum Number of Outputs

121

Unlimitedb

Maximum Skew

tSKEW

~ tSKEW + tPDc

~tSKEWd

SYNC Timing

Easy

Moderate

Easy

SYSREF Request Timing

Easy

Moderate

Easy

Moderate

Easy

Number of External VCOs

Npar

Software SYNC/SYSREF Request?

Yes

a Assumes ADC SNR equivalent integrated PLL/VCO RMS jitter contribution of 27fs and additive jitter for distribution-only parts of 70fs.

b The only limitation is the ability to distribute the reference accurately.

c Assumes worst case skew between controller and follower outputs. Dependent on propagation delay of follower and skew of controller-to-follower routing.

d Dependent on skew of reference distribution parts, reference routing, and individual part-to-part skew.

Multi-Chip Synchronization and SYSREF Generation

Using one LTC6952 in EZSync Standalone configuration

(Figure 10), up to eleven clock signals or SYSREFs can

be generated and synchronized. For applications requiring

more than eleven clock outputs, the LTC6952 supports

two methods of multi-chip synchronization and SYSREF

generation: EZSync Multi-Chip and ParallelSync. The

synchronization configuration is determined by bits EZMD

and PARSYNC, and their required settings are shown in

Table 16. Table 17 introduces the important attributes

of these methods and their variants, with further details

provided in the following paragraphs. Note that this table

only refers to two-stage applications. Many more outputs

are possible by using more stages.

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