LTC6952 datasheet(62/80 Pages) AD

62 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Charge Pump Function and Current Programming

For the parallel LTC6952s, disable all the charge pump

functions (CPMID, CPWIDE, CPRST, CPUP, CPDN, and

CPINV), allowing the loop to lock. Using Table 6 with the

previously selected ICP of 11.2mA gives CP[4:0] = h13.

SYNC and SYSREF Global Modes Programming

Bit EZMD controls whether the IC is an EZSync standalone/

controller (“0”) or follower (“1”). Since this example is a

ParallelSync application, set bit EZMD to “0”. Bit SRQMD

determines if the part is in synchronization mode (“0”) or

SYSREF request mode (“1”). SYSCT programs the number

of pulses for any output in pulsed SYSREF mode (# pulses

= 2SYSCT, so SYSCT = 2 to achieve four pulses for this

example). Combining this information with the previously

determined charge pump controls, registers h0A and h0B

can be programmed:

REF LTC6953 Reg0A = N/A

REF LTC6953 Reg0B = h04

LTC6952 #1 Reg0A = h13

LTC6952 #1 Reg0B = h04

LTC6952 #2 Reg0A = h13

LTC6952 #2 Reg0B = h04

Note that the SSRQ bits will remain “0”.

Output Divider, Delay and Function Programming

Four registers for each output allow the outputs to be

configured independently of each other. The first register

controls the output divide ratio through two control words,

MPx and MDx, as described in Equation 1.

The second register contains the control modes and the

most significant bits of the digital delay control word. The

third register contains the remainder of the digital delay

control word, and the fourth register is the analog delay.

Both the analog delay and the output invert (OINVx) bits

can be used to correct PC board layout issues such as mis-

matched trace lengths and differential signal crossovers,

respectively. Note that the use of analog delay on clock

signals will degrade jitter performance. For this example,

assume the PC board is laid out in an ideal manner and

no output inversions or analog delays are needed. With

this information all of registers h0C through h37 for all

ICs can be programmed using the information in Table

30, Table 31 (with Equation 1), and Table 32.

Reference Synchronization

In applications where the output divider values of the

reference clock outputs are greater than one, it is nec-

essary to synchronize the distributed reference signals

before synchronizing the parallel LTC6952s. To do this,

the SRQEN bits of the valid outputs on the reference

distribution LTC6953 are set to “1”, and SRQMD is set

to “0”. Set the SSRQ bit in Reg0B of the REF LTC6952 to

perform the synchronization (or drive the EZS_SRQ input

to the high state):

REF LTC6953 Reg0B = h05

After waiting a minimum of 1ms, write Reg0B again (or

drive the EZS_SRQ input to the low state):

REF LTC6953 Reg0B = h04

Note that synchronizing the REF LTC6953 will cause the

parallel LTC6952s to lose lock temporarily. Allow sufficient

lock time for the parallel LTC6952s before synchronizing

them.

At this point, the reference outputs are synchronized and

must continue to run during the synchronization of the

parallel parts. To ensure this, set the SRQEN bits of the two

reference clock outputs to “0”. Also set the SRQMD bit to

“1” to allow passthrough retiming to the reference clocks.

REF LTC6953 Reg0D = h00

REF LTC6953 Reg15 = h00

REF LTC6953 Reg0B = h0C

LTC6952 Datasheet(PDF) 62 Page - Analog Devices

LTC6952 Datasheet(HTML) 62 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL