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LTC6952 Datasheet(PDF) 54 Page - Analog Devices |
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LTC6952 Datasheet(HTML) 54 Page - Analog Devices |
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54 / 80 page  LTC6952 54 6952f For more information www.analog.com Preliminary Technical Data Advance Product Information Subject to Change Rev PrA APPLICATIONS INFORMATION Note that the SSRQ bits will remain “0” for now, but will be used later during the synchronization and SYSREF request procedures. Output Divider, Delay and Function Programming Four registers for each output allow the outputs to be configured independently of each other. The first register controls the output divide ratio through two control words, MPx and MDx, as described in Equation 1. Thesecondregistercontainsthecontrolmodesandthemost significant bits of the digital delay control word. The third register contains the remainder of the digital delay control word, and the fourth register is the analog delay control. Both the analog delay and the output invert (OINVx) bits can be used to correct PC board layout issues such as mismatchedtracelengthsanddifferentialsignalcrossovers, respectively.Notethattheuseofanalogdelayonclocksignals will degrade jitter performance. For this example, assume the PC board is laid out in an ideal manner and no output inversions or analog delays are needed. With this informa- tion, all of registers h0C through h37 for both CONTROLLER and FOLLOWER can be programmed to the values in Table 28 and Table 29, calculated using the information in Table 25, Table 26 (with Equation 1), and Table 27. Table 28. CONTROLLER Output Register Settings for EZSync Multi-Chip Design Example ADDR Value ADDR Value ADDR Value h0C h9C h1C h9C h2C h00 h0D hE0 h1D hE0 h2D h80 h0E h26 h1E h26 h2E h00 h0F h00 h1F h00 h2F h00 h10 h38 h20 h38 h30 h9C h11 h80 h21 h80 h31 hC0 h12 h2E h22 h2E h32 h2D h13 h00 h23 h00 h33 h00 h14 h9C h24 h9C h34 h99 h15 hE0 h25 hE0 h35 h00 h16 h26 h26 h26 h36 h00 h17 h00 h27 h00 h37 h00 h18 h38 h28 h38 h19 h80 h29 h80 h1A h2E h2A h2E h1B h00 h2B h00 Table 29. FOLLOWER Output Register Settings for EZSync Multi- Chip Design Example ADDR Value ADDR Value ADDR Value h0C h00 h1C h00 h2C h00 h0D h00 h1D h80 h2D h80 h0E h00 h1E h20 h2E h20 h0F h00 h1F h00 h2F h00 h10 h9C h20 h9C h30 h9C h11 hE0 h21 hE0 h31 hE0 h12 h00 h22 h1F h32 h1F h13 h00 h23 h00 h33 h00 h14 hF8 h24 h00 h34 h00 h15 h80 h25 h80 h35 h80 h16 h20 h26 h20 h36 h20 h17 h00 h27 h00 h37 h00 h18 h9C h28 h9C h19 hE0 h29 hE0 h1A h1F h2A h1F h1B h00 h2B h00 Synchronization The outputs in this example are now running at the desired frequency, but have random phase relationships with each other. Synchronization forces the outputs to run at known and repeatable phases and can be achieved in this example either externally, by driving the CONTROLLER’s EZS_SRQ± pins, or internally, with the CONTROLLER’s SSRQ bit in Reg0B. Since the part was just programmed, set the SSRQ bit to “1” and hold the EZS_SRQ± pins low: CONTROLLER Reg0B = h05 After waiting a minimum of 1ms, set SSRQ back to “0”: CONTROLLER Reg0B = h04 Once the internal synchronization process completes, the outputs will be aligned as shown in Figure 33. Note that the internal divider behavior for the muted SYSREF outputs is shown as well as the actual outputs to demonstrate the phase alignment following synchronization. Also notice that all FOLLOWER outputs will have additional delay from the CONTROLLER outputs equal to the FOLLOWER’s tPD as described in the Electrical Characteristics. |
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