LTC6952 datasheet(61/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Status Register Programming

This example will use the STAT pin to alert the system

whenever the ICs generate a fault condition. For the

two parallel LTC6952s, program x[5], x[3], x[1] = 1

to force the STAT pin high whenever any of the LOCK,

VCOOK, or REFOK flags asserts. The REF LTC6953 only

needs x[3] = 1 because it does not have a PLL:

REF LTC6953 Reg01 = h08

LTC6952 #1 Reg01 = h2A

LTC6952 #2 Reg01 = h2A

Power and FILT Register Programming

For correct PLL operation on the three ICs, all internal

blocks should be enabled. Additionally, the REF and VCO

input signals have sufficient slew rate and power to not

need the FILT or BST bits:

REF LTC6953 Reg02 = h00

LTC6952 #1 Reg02 = h00

LTC6952 #2 Reg02 = h00

Output Power-Down Programming

During initial setup and synchronization, all used outputs

and the SRQ circuitry should be set to full power. These

bits will be used later to place the ICs in a lower power

mode while waiting for SYSREF requests:

REF LTC6953 Reg03 = h00

REF LTC6953 Reg04 = hFF

REF LTC6953 Reg05 = h3F

LTC6952 #1 Reg03 = h03

LTC6952 #1 Reg04 = h00

LTC6952 #1 Reg05 = h0C

LTC6952 #2 Reg03 = h03

LTC6952 #2 Reg04 = h00

LTC6952 #2 Reg05 = h00

APPLICATIONS INFORMATION

RAO and PARSYNC Programming

PARSYNCshouldbesetto“1”forthetwoparallelLTC6952s.

Also, set RAO to “1” for the two parallel LTC6952s as this

will minimize chip-to-chip skew. A slight degradation of

in-band PLL noise will result from setting RAO to “1”.

Lock Detect Programming

Next, determine the lock indicator window from fPFD.

From Table 4 we see that LKWIN = 0 with a tLWW of 3ns.

The LTC6952 will consider the loop “locked” as long as

the phase coincidence at the PFD is within ±3ns, or 133°

as calculated below.

phase = 360° • tLWW • fPFD

= 360° • 3n • 122.88M

≈ 133°

Larger values of COUNTS lead to more accurate and stable

lock indications at the expense of longer lock indication

times. A COUNTS value of 2048 will work for this applica-

tion. From Table 5, LKCT[1:0] = 3 for 2048 counts.

R and N Divider Programming

For the reference LTC6953, the R and N values are ir-

relevant as there is no PLL. The previously determined

R and N divider values for the two parallel LTC6952s are

1 and 24, respectively. Using these values and the RAO,

PARSYNC, and lock detector values, registers 6 through

9 can be programmed for the parallel LTC6952s:

LTC6952 #1 Reg06 = hCC

LTC6952 #1 Reg07 = h01

LTC6952 #1 Reg08 = h00

LTC6952 #1 Reg09 = h18

LTC6952 #2 Reg06 = hCC

LTC6952 #2 Reg07 = h01

LTC6952 #2 Reg08 = h00

LTC6952 #2 Reg09 = h18

Note that registers 6 through 9 for the REF LTC6953 are

not applicable.

LTC6952 Datasheet(PDF) 61 Page - Analog Devices

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